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Original question:

ADS127L01: schematic request

ADS127L01: Digital ready pin not pulling low.

Jack Summers11
Intellectual 420 points
Part Number: ADS127L01

Hi,
I am having difficulty reading a voltage off of a charge couple device using the ADS127L01 ADC. My issue is that the DRDY pin never pulls low.  I am a chemist by training and have been teaching myself digital electronics for a few years, so there may be something really basic that I am missing. 

I am trying to read voltages off of a Toshiba TCD1304 CCD.  The CCD outputs data to be read every 4 microseconds. I am amplifying the signal with a rail to rail op amp and feeding it into the ADC.  I have the FORMAT and HR pins tied to ground and am using a 60.4 kohm resistor between the REXT pin and ground.  As I understand it, this gives puts me in Low Power mode with SPI.  I have the INTLDO pin pulled low with a 10 Kohm resistor and the FILTER0, FILTER1, FSMODE, OSR0 and OSR1 pins tied LOW.    I am interfacing the ADC with a TM4C123G microcontroller.  I connected the CS pin to a GPIO pin on the microcontroller that I pulled LOW, and am using the microcontroller's SPI module for MOSI, MISO and SCK.  I have the RESET pin on another GPIO that is written HIGH. I generate the clock using a pwm output from the microcontroller at 8 MHz (the clock looks good on the scope). I write the START pin LOW, give it a few milliseconds then write it HIGH.  After some time, the DRDY pin is supposed to go LOW.  That is what I am not seeing. Instead, the DRDY pin stays high.  I want to trigger ADC reads on the falling edge of the DRDY signal. 

Just saw that I have the DRDY pin on a GPIO set to be a weak pullup (perhaps the problem? I will look at this tomorrow). 

In the mean time, any ideas on how to proceed would be appreciated.

Thanks,

Jack

  • 0
    Intellectual 420 points

    Update: Commenting out the line configuring the DRDY reading GPIO pin as internal pullup did not fix the problem.  Now, however, the DRDY pin stays LOW when it should go HIGH. 

    I do not think the problem arises because the START pin is not kept low long enough; I hold it low for 300 microseconds. 

  • 0 in reply to Jack Summers11
    TI__Mastermind 46290 points

    Hello Jack,

    Usually when the DRDY line is not toggling, either the power supply voltages are not correct, or the master clock is not present.

    The ADS127L01 requires a continuous clock, and I assume you are providing this from the MCU, PWM=8MHz?

    Based on your configuration, you are using the wideband filter, and with CLK=8MHz, your output data rate will be 250ksps.

    The ADS127L01 is intended to operate in continuous conversion mode with the wideband filter; the START pin is only meant to reset the filter or synchronize readings to an external event.  If everything is powered correctly, after power-up delay, the /DRDY should start toggling at the output data rate, or 250ksps in your case, without any activity on the SPI bus.

    Please measure and confirm your supply voltages are correct.  The analog supply should be set from 2.7V to 3.6V, and the DVDD supply should be in the range of 1.7V to 3.6V.  LVDD is generated internally, and should measure a nominal 1.8V.

    If these all check out, please send a waveform capture with SCLK, /CS, MISO, and MOSI.

    One other check; make sure DVDD is powered from the same supply as your digital IO pins on your MCU.  If these are different supplies and the MCU powers-up before the ADS127L01, this could cause a latch-up condition requiring a power-cycle.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Intellectual 420 points

    Thanks Keith,

    I am powering everything off of a 3.3 volt LDO (TPS 73633) which gets power from a USB port.  Things using power include the microcontroller, ADC, 1.8 volt reference, op amp and CCD.  Perhaps the CCD is drawing more current than I am aware of.  I will check the voltages as you suggest.  You are correct about me running the master clock from the microcontroller pwm at 8 MHz.  Wave form for that looks good on my scope.  I have the CS pulled low and RESET high.  I am not trying to send data, so MOSI should be low and I am not getting data from MISO.  SCL looks appropriate, but I should probably check that to make sure the frequency is ok. 

    It is good to know that the DRDY pin should be toggling at 250 KHz.  I have found the data sheet on the ADC to less than optimal for my application and level of expertise.

    Thanks again.  I will check the voltages as you suggest.

    Best regards,

    Jack

  • 0 in reply to Jack Summers11
    TI__Mastermind 46290 points

    Hi Jack,

    Please keep in mind that DRDY will stay high after the START pin transitions low->high until the internal digital filter is fully settled.  In your case, using the wideband filter, this will take at least 84 conversion cycles, or 336uS.  If START toggles at a shorter period than 336uS, then DRDY will always stay in the high state.

    As I had mentioned before, the DRDY should toggle at the output data rate of 250ksps without any SPI activity and RESET/START held high.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Intellectual 420 points

    Hi Keith, Thank you for your help on  this.  Removing the CCD seems to have fixed the problem.  It looks like I will have to re-design the board to resolve power supply issues.

    Thanks again,

    Jack