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ADC16DV160: FPGA communication problems

Moritz H.
Prodigy 20 points
Part Number: ADC16DV160

Hello I have a problem with the ADC16DV160 which is built on an FPGA board with an Artix 7. The power supply is designed according to the specifications in the data sheet. The clock is generated directly by the FPGA and is dc coupled to the ADC. A communication via SPI is possible, I can read and write registry. The problem is the missing outclk and the missing data transfer. I also tried the test pattern but without success.

Thank you for your help.

  • 0
    TI__Guru* 91947 points

    Moritz,

    The problem is probably the clock at the ADC. Please verify that it is at the correct common mode level and amplitude. FPGA clocks are normally noisy and a bad idea to use as a clock source for an ADC. Is the clock terminated properly?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 20 points

    Hello Jim,

    thank you for your answer. The clock has the correct common mode level an proberbly also the correct amplitude. Here the datasheet is not so specific with the minium required amplitude levels. The clock is terminated in the FPGA and differentially routed to the ADC and has also the correct impedance. Is an additional termination resistor required for the adc?

    Best regards,

    Moritz   

  • 0 in reply to Moritz H.
    TI__Guru* 91947 points

    Moritz,

    The clock input should be like what is shown in Figures 33 or 34 of the data sheet. The output clock requires 100 Ohm termination across the + and - signals as close as possible to the load. The power needs to be sequenced per the "Supplies and Their Sequence" section of the data sheet on page 24. Verify all supplies are at the correct voltage level.

    Regards,

    Jim