Other Parts Discussed in Thread: TINA-TI
Hi!
We have problems regarding the basic application of ADS7042 SAR ADC. We are attempting to design proof of concept circuit on breadboard. Because of this SCLK frequency has been reduced to 20 kHz to avoid breadboard related problems.
As ADC driver we are using the recommended operational amplifier OPAx835 configured as non-inverting amplifier with gain 10, which is also used to bias the input voltage of ADC to 0.5×AVDD. Output of op-amp is behaving as expected (measured with oscilloscope, at open circuit and 10 kΩ resistive load) hence we believe that it poses no problems. However we've encountered great difficulty with running the ADC following the driver.I will describe the setup and problems in detail.
ADC is in VSSOP package so we're soldering it, by hand using hot-air gun, onto homemade VSSOP-to-DIP adapter for prototyping purposes and placing it onto the breadboard. Supply voltages AVDD and DVDD are the 3.3V regulated using the same LF33CV linear voltage regulator and decoupled with 0.33 μF and 100 μF capacitors. Oscilloscope measurements have shown no significant ripple on those voltages in any case thus we believe that powering the chip isn't a problem. ADC should be communicating via SPI to the Arty Z7-20: SoC Zynq-7000 FPGA board (which uses 3.3V logic). However, it's behavior is unusual in the following sense: ADC SDO output pin generates some (actually meaningful, falling-clk-edge changing) signals at almost random data frames. However, when plugged into FPGA input pin the signal is lost (almost 0V). Appropriate FPGA pin is configured as input pin as verified using different SPI peripherals. AINM pin is grounded. AINP pin when open presents 3.3V DC level; and also when connected to the output of the driver this voltage persists. Only idea we had is that the ESD diode to AVDD was somehow blown-shorted.
Any help regarding what may be causing this issue will be greatly appreciated!
Also i would like to ask several questions which may help to resolve the issue in the following attempts:
1. Does the order of applying (a) power supply AVDD and DVDD voltages, (b) signal voltage and (c) digital SPI communication signals matter in any way? Especially, would applying 3.3 V on CSZ before DVDD or AVDD damage the chip?
2. Would series resistors on SPI lines featured in some reference designs be important to anything but impedance matching at high frequencies? Also, should SPI lines be pulled-high or pulled-low (it appears that the documentation doesn't state this)?
3. Would connecting DVDD pin to VDD pin of FPGA be appropriate solution for digital supply?
4. Should SCLK clock be active ("ticking") during the CSZ high logic state (as shown in TINA-TI example simulations and some reference designs) or can it be deactivated during that period?
If you need any additional information please ask. Thank you for your time and thanks in advance!
Best regards,
-- D. Đ.
