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ADS1252 The first DRDY after sync start is earlier than the datasheet.

user6365974
Prodigy 210 points
Part Number: ADS1252
problem:
The first DRDY after synchronization starts is earlier than the data sheet. Is this normal?
In the data sheet, DRDY (t14) after the start of synchronization is 2045.5*CLK, but at present it is (calculated) 314*CLK.

Situation:
There is one device and CLK is 500KHz.
Since it is necessary to synchronize for the convenience of the system, we are synchronizing to one device.

I will attach an image.
1ch (yellow): SCLK
2ch (blue): DO/DRDY
1. Synchronous mode is started by inputting SCLK HIGH during 4*tDRDY.
2. DRDY has arrived earlier than the data sheet since SCLK went LOW.

1:

2:


Question:
1. Is this normal and is sync mode enabled?
2. If the phenomenon that t14 becomes faster is an abnormal operation, is there a cause?

  • 0
    TI__Mastermind 44881 points

    Hi User,

    Here is a link to another e2e post about this topic with some helpful information.

    Since you only have 1x ADC in your system, are you using SYNC to align the conversion with an external event? Please note that the time t14 only has a typical value, and can vary widely, so I am not sure this is the best approach. I would not recommend using the sync mode with a single ADC.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 210 points

    HI Bryan

    >Since you only have 1x ADC in your system, are you using SYNC to align the conversion with an external event?
    That's almost right.
    -We are considering using the synchronous mode for the purpose of acquiring data at the specified timing.
    ・It is expected that there will be a sample hold circuit in front of the ADC input to control the timing.
    ・I also tried the power down mode. This is as per the data sheet.
    *We are diverting the existing system and doing this kind of work.

    Takayuki

  • 0 in reply to user6365974
    TI__Mastermind 44881 points

    Hi User,

    Did the link to the e2e post help solve any challenges you might be having?

    -Bryan

  • 0 in reply to Bryan Lizon86
    Prodigy 210 points
    HI Bryan
    I saw the posted post. (This post is not clear if the issue is resolved)
    We believe that our timing meets t13 (1537-7679*CLK), which is the condition to enter the synchronous mode.
    (I measured the current t13, but it was 6.23ms, that is, 3115*CLK (3.23ms/2us=3115*CLK))
    It's not surprising that it can fluctuate significantly,
    -It is not recommended to use synchronous mode with one ADC.
    ・There is no problem in power down mode.
    ・Use other methods to improve the timing.
    Based on the above, we will consider other than the synchronous mode.
    Takayuki