Hello,
I'm using an FPGA to interface with the ADS7953 device and I would like some clarifications on the timing of SDO and SDI.
- It seems like SDI should be available before the first rising edge of SCLK after CS_N is low, and SDI should change on the falling edge of SCLK, correct?
- Make sure CS_N has been high for at least 20 ns (to satisfy tw_1), then assert CS_N
- After CS_N falling edge, wait 30 ns (to satisfy both td_1 and tsu_1 at VBD=3V) and enable the first rising edge of SCLK.
- Upon falling edge of SCLK
- wait 10 ns (to satisfy th_1 at VBD = 3V), then latch in SDO
- increment the falling edge counter until it reaches 16
- Once all 16 bits have been captured, wait for at least 20 ns (to satisfy tq - tw_1) and pull CS_N high
- Go back to step (a)
Any help is appreciated. Thank you.