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ADS7953: Clarification on SDO and SDI timing

Vu Dang
Prodigy 10 points
Part Number: ADS7953

Hello,

I'm using an FPGA to interface with the ADS7953 device and I would like some clarifications on the timing of SDO and SDI.

  1. It seems like SDI should be available before the first rising edge of SCLK after CS_N is low, and SDI should change on the falling edge of SCLK, correct?
It's not clear to me which edge of SCLK SDO will change on, the datasheet does not make this information explicit, but I assume it is the falling edge,. I would like to know if my current implementation is correct.
  1. Make sure CS_N has been high for at least 20 ns (to satisfy tw_1), then assert CS_N
  2. After CS_N falling edge, wait 30 ns (to satisfy both td_1 and tsu_1 at VBD=3V) and enable the first rising edge of SCLK.
  3. Upon falling edge of SCLK
    1. wait 10 ns (to satisfy th_1 at VBD = 3V), then latch in SDO
    2. increment the falling edge counter until it reaches 16
  4. Once all 16 bits have been captured, wait for at least 20 ns (to satisfy tq - tw_1) and pull CS_N high
  5. Go back to step (a)

Any help is appreciated. Thank you.

  • 0
    TI__Mastermind 25020 points

    Hello,

    Your assumptions are correct, the SDO and SDI change state at falling edge of SCLK and should be read at the rising edge of SCLK. SDI is also available with CS falling edge, as you noted.

    You need to wait minimum of t_su1, and by the max t_su1 to get SDO out, thus 30ns should be sufficient.

    As for when to read the data, you can wait minimum of t_h1, or you can use the rising edge of SCLK to read the data.

    Step four, this does meet timing requirements. 

    But I would like to point out that you do not need to subtract the two times. The CS signal can be brought up high anytime after 16 falling edge.

    Time t_w (20ns) is stating the minimum CS high time.  Time t_q (40ns) is stating that CS cannot have a falling edge until the minimum time is met, but it can go high before.

    This means that CS can be high 1ns after 16 falling SCLK, be high for 39ns, and the timing requirements are met. Another example as after 16 SCLK falling edge, waiting 40ns to bring CS high, and then wait 20ns with CS high before bring it back down.

    Both these example meet the timing requirements

    Regards

    Cynthia