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ADC32RF80EVM

Other Parts Discussed in Thread: ADC32RF80EVM, TSW14J57EVM, ADC12DJ3200EVM, LMK04828BEVM

Hi TI Engineer:

Question 1: Regarding ADC32RF80EVM board, the recommended data acquisition card in the description on TI official website is TSW14J56EVM. Can I use TSW14J57EVM data acquisition card for sampling?Meanwhile, regarding ADC12DJ3200EVM board, the recommended data acquisition card in the description on TI official website is TSW14J57EVM. Can I use TSW14J56EVM data acquisition card for sampling?Do you have any problems with this match?

Question 2: Due to special needs, now it is necessary to stitch two ADC32RF80EVM boards with 3G sampling rate to achieve the effect of 6G sampling rate (two chips are sampled alternately). Is this possible if I use LMK04828BEVM boards for clock control of two boards?The main concern is the control accuracy and response time of LMK04828BEVM.How much error can this scheme achieve?

  • With regards to using ADC32RF80EVM with TSWJ5x boards: yes you can use J57 board instead of J56 since the max SerDes rate (out of ADC32RF80EVM) is 12.5Gbps or lower. J56 supports a SerDes rate up to 12.5Gbps whereas with J57, it can be as high as 15Gbps. 

    I think the same holds for ADC12DJ3200EVM. You can check asking that in a different thread addressed to that support team.

    It looks like you're planning to clock ADC32RF80EVM externally, sourced from LMK04828EVM. That should work, assuming the enough drive strength to avoid SNR degradation. In our earlier tests, LMK's insufficient drive strength above 2.5GHz resulted in poorer SNR. The swing requirement on the clock inputs are specified in the datasheet. The accuracy will depend on how you route between the respective EVMs, drive strength will have an adverse effect. A better option might be to clock the ADC with the on-board LMX chip and provide a common reference to the two EVMs. Then you won't have the drive strength issue in addition to the advantage of working at a lower frequency (to synchronize the EVMs).   

    Satish.