ADC12DJ3200: Deterministic Latency : SYSREF setup & hold

user5163865

Part Number: ADC12DJ3200

Hi,

I received the following questions from a customer.

Q1. If SYSREF and DEV_CLK phases (setup, hold) do not meet the data sheet specifications, how much does Latency fluctuate? Is it about several clk of DEV_CLK?
On our current system, the JESD204B Latency varies with each power OFF/ON.

So I'm looking at this material.

/ /tidu171.pdf

According to "3.1 Requirement 1: Aligning the LMFCs and Meeting SYSREF Setup and Hold Requirements"

In order to estimate Deterministic Latency, I think it is essential to meet the setup and hold conditions.

Therefore, I find it difficult to answer this question. Is it correct?
If TI has an answer to this question, would you please answer me?

Regards,

Hiroshi

over 5 years ago

0 Neeraj Gill over 5 years ago

TI__Mastermind 20541 points

Hi Hiroshi,

Yes your assumption is correct. Aligning the LMFCs and Meeting SYSREF Setup and Hold Requirements" is required.

Please take a look at section mentioned below from the datasheet. It show how to achieve deterministic latency. There is SYSREF calibration feature on ADC will be help with meeting the setup and hold time.

7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency

Regards,

Neeraj

0 user5163865 over 5 years ago in reply to Neeraj Gill

Genius 3980 points

Hi Neeraj,

Thank you for your reply.

Regards,

Hiroshi

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ADC12DJ3200: Deterministic Latency : SYSREF setup & hold