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ADS1298 SPI set up

Adam Freed
Prodigy 215 points

Other Parts Discussed in Thread: ADS1298

Hello,

I am try to set up my ADS1298 via SPI through a PIC24F mcu.  I am using the internal clock and have start and clksel tied high.  I am following fig.63 on p.69 at power up with respect to the reset signal.  I then send the stop data continuous command, followed by WREG CONFIG3 0xC0 as described in fig.64 on p.70.  Finally, I am simply attempting to read the contents of the ID control register, but after issuing the command, have not seen the output.  Am I missing something?

A few other things to note:

- DOUT stays high for two SCLK cycles on every issued command.

- DRDY goes high for a while during and after issued commands.

- DOUT and DRDY periodically toggle after power up.

- Are there any time restrictions between sending opcodes of the RREG command? 

- Are there time restrictions for toggling SCLK to receive the output of the RREG command after sending the second opcode?

- My SCLK period is ~100us, is this a problem?

Thanks,

Adam

  • 0
    TI__Guru**** 183381 points

    Hi Adam,

    There are a few other posts here from folks asking questions about reading the device ID register.  You might want to take a look at these:

    While I can't really help you out with code for the PIC 24F, you might try posting a screen shot of the communication transfer to let us verify the correct data/clock phase relationship is being used.  You 100us clock is going to be a problem depending on how you configure the ADS1298.  The MAX SCLK clock of 20MHz is listed in the data sheet by means of noting the minimum period (tsclk min = 50ns).   Consider the fact that the ADS1298 has eight simultaneously sampled channels.  To retrieve all data from the part, you need the 24-bit status word and the eight 24-bit conversion data words.  So, you are looking at (9*24*100us) = 21.6ms to retrieve a complete series of conversion results.  ' not going to get you much throughput, but should be fine if you intend to run the single-shot operating mode.

    There are some limitations on sending opcodes, some must have at least 4 master clock cycles between them for proper decode, but I don't think that's an issue here.  If you are not configuring the part for single-shot mode, the DRDY may be toggling during your SPI transmission do to the low SCLK speed.

  • 0 in reply to Tom Hendrick
    Prodigy 140 points

    Hi, Tom I am needing an example code for programming ads1298 by spi interface

     

    Because I have same problem with registers configuration.

     

    Another question is: how  spi interface can acquire data from 8 simultaneos channels with 24 bits per channel.

  • 0 in reply to german Catalini
    TI__Mastermind 46290 points

    Hello Catalini,

    I do not have as much DSP SPI wisdom as Tom, but a lot of times when customers have SPI questions we have them make sure they have their SPI clock phase and polarity set correctly.

    As for your other question though, the SPI interface returns 216 bits for a RDATA or RDATAC op code. You get back a status word followed by 8 channels of data. So it takes several SPI frames to return all of the data. This is documented on page 42 of the ADS1298 datasheet for the RDATA case. Figure 37 on page 32 breaks down the 216 clock cycle some more.

  • 0 in reply to Tom Hendrick
    Intellectual 835 points

    HI Tom, How are you?

    Tom I have the following question, the minimun sclk period is 2MHZ=50ns? I can't use sclk 580khz clock?

    Thanks 

  • 0 in reply to Oscar Baumann
    TI__Mastermind 46290 points

    Oscar,

    The spec is for the minimum sclk period, as period gets smaller frequency increases. A 50ns minimum period means the maximum frequency is 20MHz. If you wanted a 580kHz clock the period would be about 1724 nanoseconds, well above the minimum period.

  • 0 in reply to Kevin Duke
    TI__Mastermind 46290 points

    Oscar,

    Another quick note...your data rate is going to be more limited as you use a slower sclk, as is the case with any converter.

    You should take special care with the ADS1298 though, since each DRDY pulse out of the ADS1298 requires that you read 9 24 bit words (a status word plus channel data, total of 216 bits). So with a 580kHz clock the maximum data rate you can achieve is 2kSPS. With any higher data rate you're going to be in the middle of reading data from the part when DRDY pulses again and loads the next samples data into the data registers, which would corrupt the data you were in the process of reading.