• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 48 subscribers
  • Views 789 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

timing sample edge (TSB12LV32-EP)

Torben Rasmussen
Prodigy 110 points

Other Parts Discussed in Thread: TSB12LV32-EP

Hi

Data sample in and out of the microcontroller interface is this related to the BCLK clocked or the event of teh RW and CS signals.

 

If the data is clocked on the edge of BCLK what clock periode will be the valid clock edge if the data and control signals are all valid for more then one cycle.

Is it only the first, both or last clock edge?

 

Thanks

Torben Rasmussen

  • 0
    TI__Guru 62930 points

    These will depend on your configuration.

    Please see section 3.3 of datasheet for description of interface.  http://www.ti.com/lit/gpn/tsb12lv32-ep

    Regards,

    Wade

     

  • 0 in reply to Wade Vonbergen
    Prodigy 110 points

    I have the datasheet (TSB12LV32-EP SGLS139B october 2003- revised April 2004) But i might have over looked the information. The datasheets states on page 29 that the data on the bus is valid when MCS and WR are both low. I assume that it should say shall be valid if both MCS and MWR are both low.

    If this is the case i assume that the data only needs to be stable for the last rissing clock edge as long as MCS and MWR are valid. Or is it only the first rising edge of the clock.

    Thanks

    Torben Rasmussen

     

  • 0 in reply to Torben Rasmussen
    TI__Guru 62930 points

    Torben,
    I believe it is the first clock.
    Take a look at the read timing diagram.  MD becomes valid as result of first BCLK after MCS.

    Similarly,  during write MCA will assert after first BCLK.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 110 points

    OK But if you extend this last cycle to two. what edge is it then. Clock cycle event list.

    1st first rising edge of BCLK, MCS and MWR is low and detected.

    2nd rising edge the data is then sampled. (MWR and MCS is stil low.

    3th rsing MWR and CS is stil low is the data then sampled again?

    4th rising edge MWR and CS is now high, data is not sampled.

     

    The problem is the 3th rising edge is the data sampled on this edge also and replaces the data from 2nd rising edge?

    The CPU controlling the interface have a bad timing so the data might disapere before CS and WR is high again but is held low for one cycle minimum.

    Also see the attached file for illustration.

    Regards

    Torben Rasmussen

    7077.TSB12LV32-timing-question_TI.pdf

  • 0 in reply to Torben Rasmussen
    TI__Guru 62930 points

    Torben, I will need to locate some design information to get complete answer.

    I will post here when I  have answer.

    Thanks,

    Wade

  • 0 in reply to Wade Vonbergen
    TI__Guru 62930 points

    I was able to confirm my assumptions.

    This would be tp1 in your diagram.

    Data will be valid on the first rising edge of BCLK after MCS/ and MWR/ are low, so it should be tp1.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    Prodigy 110 points

    That i do not understand, this is for a write cycle. 

    at tp1 the MCS and MWRn is sampled low

    From your answer is read that it always samples data and then evaluates if MCS/ and MWR/ is valid else it is not possible for it to sample data at the same clock edge?

    And data is not sampled on the following rising edge tp2 and tp3 where MCS/ and MWR/ are still low?

     

    Best regards

    Torben

  • 0 in reply to Torben Rasmussen
    TI__Guru 62930 points

    Torben, the device has different setup times for control vs data bus.

    It is possible to capture data bus at tp1 based on MCS/MWR.

    Regards,

    Wade