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ADS1260: SPI timming and how to deal with unused-pins(AIN2/3/4,COM)

Noriyuki Takahashi
Genius 11230 points
Part Number: ADS1260
Other Parts Discussed in Thread: ADS1261

Hi team

Customer has several questions related to ADS1260. Could you help to answer on these?

1.  The attached is the SPI timing they expect at 10SPS. Could you please review the timing is correct?

2. AIN2/3/4, COM are not used in their system and those are connected GND. In the datasheet, it is recommended that to minimize input leakage of the measurement channel, tie unused inputs to mid-supply voltage (AVDD + AVSS) / 2 or to AVDD, but could you tell what will happen if those are connected to GND?

And could you also tell what the input leakage increment will bring to the system?

Regards,

Noriyuki Takahashi

  • 0
    TI__Genius 11230 points

    Sorry. I forgot the attached timing diagram.

    タイミング.pdf

  • 0 in reply to Noriyuki Takahashi
    TI__Mastermind 44720 points

    Hi Noriyuki-san,

    I can assist.

    1. I have the following comments regarding the timing diagram:
       
      1. Unless the ADS1260 is to be used in single-shot mode (i.e. where one conversion is completed and then the ADC stops and waits until the MCU requests a new conversion), the START pin can be held high. In Figure 4 of the datasheet, the START pin is pulsed low to indicate the minimum LOW time but this is not a requirement! After START goes HIGH, the customer has the option to leave it HIGH (to perform continuous conversions) or return it LOW (to perform one conversion and stop).
         
      2. Note: After START goes high, there may be two fCLK periods before /DRDY goes high.
         
      3. The FIRST conversion result of the ADS1261 always takes longer due to the digital filter settling. Therefore, you will see from the time START goes HIGH to when /DRDY goes LOW, there will be a delay of t(STDR), as indicated by Table 8 in the datasheet. For all of the conversion results that follow, the time between /DRDY falling edges will be 100 ms (assuming a data rate of 10 SPS and a clock frequency of 7.3728 MHz).
         
      4. Note: The START pin does not need to go LOW after the /DRDY falling edge unless you want to stop the next conversion. If it goes low after 100 fCLK cycles then one more conversion will complete before the ADC stops.
         
      5. /CS may go low any time after the /DRDY falling edge. However, sooner is better since it allows you the most time to clock out the data before the next /DRDY falling edge.

      6. If the START pin is LOW, you may choose to set it HIGH any any point in time to begin a new conversion. Note that toggling the START pin like this may change the output data rate depending on when it is toggled.

    2. There is no problem with tying unused inputs to GND. However, there may be a slightly larger leakage current (on the order of tens of pA's to few nA's) flowing from AVDD to GND through the NMOS transistor of the CMOS transmission gate. We've found that tying unused inputs to a higher voltage potential generally results in a slightly lower leakage current. Tying to unused inputs to AVDD minimizes the NMOS leakage but increases the PMOS leakage. Tying to a mid-supply voltage minimizes the overall combined leakage current of the NMOS and PMOS transistors.