ADS54J64EVM: Device Clock and Sysref phase relation

Hirano,

I had the LMK experts look at the two configuration files and they replied with the following message below. They also sent me an updated config file (attached). Four registers were slightly modified. These are the ones with comments added. If you have more questions regarding this, please post them on the high speed clock forum.

Regards,

Jim

First, something’s weird with original LMK04828_config2_983M.cfg. The file says that OSCin frequency is 61.44MHz, and the OSCin clock is set as if for 61.44MHz, but the VCO divider is 24 with a prescaler of 2 (2949.12/(2*24) = 61.44MHz), and the PLL2 R-divider is set to 2 with the OSCin multiplier disabled (61.44MHz/2 = 30.72MHz), so the phase detector frequency doesn’t match. And if I assume that the VCXO frequency on OSCin is actually 122.88MHz, things make sense again (except the setting of 0x162 which is now incorrect, and could cause problems for the system with VCO calibration). The new file sets this correctly. I don’t think that causes the issue you see, but it’s something that needs to be addressed. I’m going to assume the VCXO frequency is 122.88MHz in all cases, in which case set 0x162[4:2] = 0x1.

It makes sense to me that the files have a delay difference. The old file has the device clock digital delays set to CNTH=5, CNTL=5, and SYSREF set to bypass. The new file has digital delay disabled on all the clock outputs, CNTH=5, CNTL=5, and the SYSREFs are both set to bypass mode. Both files have the same SYSREF digital delay values. The digital delay values are going to be different by 10 VCO cycles, ± whatever the difference is for enabling digital delay in the first place. The customer measurement indicates about 2ns of difference, which at VCO=2949.12MHz corresponds to about 6VCO cycles of delay difference – I can’t totally account for the 10 vs 6 difference, but I suspect there’s a static offset between enabling/disabling digital delay on a divider.

The easiest way to make the files behave the same is to turn on your digital delays (0x106 = 0x70, 0x10E = 0x70). Also, the new file should write 0x143 as 0x91 instead of 0x11 the first time, to ensure that SYSREF_CLR is set and the SYSREF digital delay counter gets reset when you power on the SYSREF_DDLY block.

I saw a question in the new file comments, so to address that line: New file can write 0x140 0x01 in sync procedure, doesn’t look like you ever use the SYSREF pulser so power it down to save current. The SYSREF_PD and SYSREF_DDLY_PD blocks can (and for SYSREF_PD, must) stay on without disrupting operation.

LMK04828_config2_983M_new_DPupdate.cfg