• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 382 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12DJ3200EVM: After giving analog sine as a input , seeing noise instead of sine wave

Deepak K1
Prodigy 190 points
Part Number: ADC12DJ3200EVM

Hi,

  I am doing interop test using AD12DJ3200 with microsemi Polarfire FPGA. I have configured ADC for JMODE2. I set JESD TEST Mode to Normal operation (default) , giving analog input 1vpp , 1MHz sine wave. But i am observing noise instead of Sine wave. In ADC GUI i am just setting Fs =1250Mhz, clock source is on board and JMODE is JMODE2. Is this setting enough or do I need to do any other settings in ADC GUI?

I checked ADC register status (208) , link is up and PLL locked. Even I have tried other test modes like Ramp test mode and transport mode. These modes are working fine. When I am giving analog input from function generator instead of sine wave i am seeing noise. Please provide sugggestions to proceed further.

Is any configuration settings am I missing?

  • 0
    TI__Mastermind 20541 points

    Hi Deepak,

    1. JMODE2 is dual channel mode can you please make sure you are applying the analog input to correct channel.

    2. When you are changing test pattern mode from ramp to normal mode can you please confirm you are disabling the JESD block Enable before making the change and enabling it afterwards?

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Prodigy 190 points

    Hi Neeraj,     

     Thanks for reply. 

     1. JMODE2 is dual channel mode can you please make sure you are applying the analog input to correct channel.

     I have connected my cable which is coming from function generator to VINA (single ended input) of ADC.

    2. When you are changing test pattern mode from ramp to normal mode can you please confirm you are disabling the JESD block Enable before making the change and enabling it afterwards?

    Yes. I am disabling JESD block enable and then changing the test mode and again enabling it.

     

    Thanks

    Deepak