ADS1258: Single-ended input resistance

Hi Carlo,

Check on Figure 37 and the accompanying description about the ADC input structure on page 16 of the ADC datasheet. This shows a simplified capacitor network to model the ADC inputs, as well as the corresponding resistive equivalent at fCLK = 16 MHz. Note that the equivalent resistance will change with clock frequency as described in the datasheet. Also note that the ADC always takes differential measurements (ADCINP - ADCINN), even when measuring ground referenced signals. So differential input impedance is usually more appropriate here, and for high impedance sensors we would recommend a buffer.

I have copied Figure 37 below for reference. Let me know if this helps answer your question.

-Bryan

Hi Daniel,

Answers to your questions:

1. As I mentioned to Carlo, the ADC always takes differential measurements (ADCINP - ADCINN), even when measuring ground referenced signals. So both switches are active for all measurements
2. As the datasheet says, capacitor CB is discharged to 0V which is the voltage seen by the inputs (ADCINP - ADCINN)
3. Are you using a 33 kHz crystal or clock oscillator? If you use a crystal it should be 32.768 kHz. If you are using an external clock oscillator we would recommend 16 MHz. You will see this as a reference value for most of the datasheet parameters that do not involve the crystal. The typical resistance values depend on fCLK, as described in the datasheet on pg. 16: "if fCLK is reduced by a factor of two, the impedances will double"
4. This is also described in the datasheet on pg. 16: "This two-phase sample/discharge cycle repeats with a period of tSAMPLE = 2/fCLK".

-Bryan

Hi Daniel,

Answers to your questions below:

• Yes, you are correct, each input is at approximately AVSS+1.3V when S2 closes
• fCLK is the master clock, and should not be confused with the crystal frequency. If you are using a 32 kHz crystal, this is applied to an internal PLL & oscillator circuit such that fCLK is 15.729 MHz. If you are using an external oscillator, we recommend a 16 MHz clock. This is described on pg. 17 in the datasheet. The values in Figure 17 are calculated using a 16 MHz fCLK frequency, as shown. If you are using a crystal, then your fCLK is 15.729 MHz, and the resistance values can be calculated accordingly based on the 16 MHz values. I would also recommend against using a crystal, since there are many startup issues other customers have seen. You can search E2E to get an overview of these challenges. Instead, I would recommend a 16 MHz clock oscillator
• Again, fCLK is not the crystal frequency, as described above. At fCLK = 15.729 MHz, tSAMPLE = 127ns.

It might help if you could explain what you are trying to do with the ADS1258. It is unclear why this information is necessary, so maybe if I understood how you were going to use this device I could provide better support

-Bryan

Hi Daniel,

Yes, your results thus far indicate that buffering would likely be necessary for your circuit, especially with 12k impedance at the input. I would highly recommend considering adding a buffer

fCLK is the master clock, and should not be confused with the crystal frequency. If you are using a 32 kHz crystal, this is applied to an internal PLL & oscillator circuit such that fCLK is 15.729 MHz.This is described on pg. 17 in the datasheet.

-Bryan