ADC3444: Vhdl or verilog reference design

Part Number: ADC3444

Hello,

We want to interface the ADC3444 with a FPGA Ultrascale+ from Xilinx. The ADC work in 2 wires mode with a frame clock which encapsulates 2 samples.

We saw the application note from Xilinx which describes a deserialization 1:7 but with a frame clock which encapsulate only 1 sample.

Do you have any reference design to interface this ADC in 2 wires mode with a FPGA?

Many Thanks for your help

Fabien