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ADS1018-Q1: Can the DOUT/DRDY still provide data-ready indicate when the CS is pulling high?

Ted Zhang
Intellectual 2280 points
Part Number: ADS1018-Q1
Other Parts Discussed in Thread: ADS1118

HI Team,

There are some contradictory in our datasheet, in section 8.5.2 chip select it says "When CS is taken high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state. In this state, DOUT/DRDY cannot provide data-ready indication."

However in P25 it says clear the CS to high and wait the DRDY to transition to low indicating the data is ready to read.

So question:  Can the DOUT/DRDY still provide data-ready indicate when the CS is pulling high?

Thanks

  • 0
    TI__Guru** 113765 points

    Hi Ted,

    I'm not sure what you are referring to on page 25, but the answer is CS must be low to be able to see the state transition from DOUT/DRDY high to low.  Some customers will permanently tie CS low, but the best method is to toggle CS after each communication transaction. 

    If you are referring to the Pseudo Code Example in section 9.1.6, I agree that it is not totally clear when it says 'clear CS to high'.  What might be better is to say toggle CS from low to high to low before DOUT/DRDY goes low again.  The point of setting CS high is to clear any potential issues with spurious signals that might affect the communication, but it must go low again to monitor DOUT/DRDY for end of conversion.

    To prevent the DOUT/DRDY pin from floating, either an external pullup resistor can be used, or the internal pullup of the ADS1118 can be used by setting the PULL_UP_EN bit high in the configuration register.

    Best regards,

    Bob B