ADS4246EVM: Example Code for ADS4246EVM

Dear Jim,

TSW1400EVM uses Altera FPGA. I am using Xilinx. Therefore I cannot use it.

I want to ask some questions about SPI configuration.

I can get the correct data when I use  TEST PATTERNS. I send the data through SPI as follow:

Input CLK = 50MHz

Address > Value

0x25 > 0x02 (All ONE)

0x2B > 0x03 (Toggle)

0x42 > 0x08 (Enable Digital)

I got the following output

I assume that my IP core for ADS4246 is working fine.

Then I want to test with a read Analog Signal to chip.

Which kind of configuration should I do through SPI?

Now I got the data but all signals are in square shape while actual signal is sign wave.

I set the dataformat (0x29 > 0x03  Offset binary).

I would like to know the correct procedure of SPI configuration to ADS4246 chip.

Please advise me.

Thanks.

Regards,

Thiha Kyaw 

Thiha,

Please do a soft reset after power and clocks are applied. Set bit 1 to "1" in register 0x00. This is a self clearing bit.

Next, I would suggest changing the format to offset binary, address 0x29 data 0x18. Above you mention a data value of 0x03 for this register which is wrong.

If you are really writing 0x18, try 2's complement by setting this address to 0x00.

Regards,

Jim 

Dear Jim,

I retest again with your suggestion.

Datasheet says we should get 10101010101010 and 01010101010101 alternatively.

But I didn't get it. 

Please advise me how to get it.

Thanks.

Regards,

Thiha Kyaw

Thiha,

Both address 0x25 and 0x2B need to be set to 0x03 for alternating 10 patterns. After writing to these registers do a read to verify they have the correct value. And register 0x42 must be set to 0x08.

Regards,

Jim

Dear Jim,

I believe the error is in IP core I develop. The reading at bit 14 of Even is not correct. Can you suggest me how I can solve it? 

Thanks.

Regards,

Thiha Kyaw

Thiha,

Are you using the part in CMOS output mode? Is the data mapped properly in your firmware? I would check your pin assignment on the FPGA side.

Another thing to try is swap the assignment inside the FPGA and see if the problem moves to the B side. If it moves then the problem might be the data coming from the ADC. Check the connector for a bent or broken pin if this is the case.

Regards,

Jim  

Dear Jim,

I use DDR LVDS Output.

After swapping the pin assignment inside FPGA, the error bit moves to swapped pin accordingly. It means the output from ADS4246 to FPGA pin has problem.

The error only occurs only when the data transition at postive clk edge. Reading data from FPGA at negative clk edge is correct.

Please advise if you have any suggestion. I will try my best to solve the problem also.

Thanks.