This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV5631: Logic Input Levels and POR Sequence

Part Number: TLV5631

  1. I cannot find a spec for the logic input levels. I want to run the DAC on 5V but control it with a 3.3V CPU. Please advise the logic thresholds for the digital inputs.
  2. In the application information section regarding POR, it says "On power up, all latches including the preset register are set to zero, but the DAC outputs are only set to zero if the LDAC is low." but then it also says "All digital inputs must be logic low until the digital and analog supplies are applied." So it would seem the if I follow the require that all inputs must be low at POR, then the the DAC outputs will always be set to zero at POR because LDAC has to be held low. Please clarify.

Thanks,

Julia

  • Hi Julia,

    1. The VIH and VIL levels are described in the recommended operating conditions table.  It should be good with 3.3V logic on a 5V DVDD supply.

    2. I am not sure why they worded this so confusingly.  In regards to the statement that "all inputs must be low at POR", what they are trying to describe is if the inputs are high before the device is powered, the ESD cells will activate and potentially power up the device or damage it.  That does not necessarily mean that the digital inputs must be ground at startup.  You could, for example, connect LDAC to DVDD, so they ramp together.  LDAC would never be greater than DVDD in that case.  

    That being said, I think it would be an okay use case to hold LDAC low at startup, as then the DAC output will be in a known state.  

    Thanks,

    Paul

  • Ah, I was looking in electrical characteristics, didn't think to look at recommended operating conditions!

    I assumed that's what was meant for the POR sequence but wanted confirmation.

    Thanks,

    Julia