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ADC12DJ3200: ADC12DJ3200 initialize stable time requirement before FPGA is configured.

Joseph Xu
Prodigy 170 points
Part Number: ADC12DJ3200
Other Parts Discussed in Thread: LMK04828, LMX2582

I have a question about the initialize stable time for the ADC12DJ3200 before FPGA is configured.

At first, I use a USB-SPI adapter to configure the LMK04828, LMX2582 and ADC12DJ3200, and then configure the FPGA, everything goes well.

Then I use FPGA to generate SPI signals to configure the LMK04828, LMX2582 and ADC12DJ3200, that means after the FPGA is configured, all 3 chips is configured sequencially, and then the JESD204B is ready to work. I assume this will work. Actually not. Because I ran an PRBS23 test, which appears No Link. The clock is OK, I can see 3.2GHz via Spectrum. And I can see SYSREF also.

The only difference between the above two method is: The time between SPI using USB-SPI adapter and FPGA configuration is about several seconds. While the time between SPI using FPGA logic and JESD20B RX logic maybe immediately. So I'm guessing is there ADC initialize stable time requirement that I need to add several us/ms delay bebore the JESD204B RX is ready to work?

BTW: the SPI clk is 1MHz, S configure timing order is:When FPGA is configured,wait 100ms，then configure LMK04828(~126ms), LMX2582(~48ms), LMK04828(~9ms),ADC12DJ3200(~18ms), just like this picture:

the register map for PRBS23 test is provided.

ADC12DJxx00
0x0000 0xB0 // Do soft reset
0x0200 0x00 // Clear JESD_EN (always before CAL_EN)
0x0061 0x00 // Clear CAL_EN (always after JESD_EN)
0x0201 0x03 // Set JMODE3
0x0202 0x13 // Set KM1=19 so K=20
0x0204 0x06 // Use TMSTP input, offset binary data, scrambler disabled
0x0205 0x03 // Set PRBS23 Test
0x0023 0x01 // Enable ADC Test
0x0213 0x07 // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples
0x0048 0x03 // Set serializer pre-emphasis to 3
0x0061 0x01 // Set CAL_EN (always before JESD_EN)
0x0200 0x01 // Set JESD_EN (always after CAL_EN)
0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine
0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration

Regards

Joseph

  • 0
    TI__Mastermind 18095 points

    It is a bit tricky to answer.  There may be some time needed for the individual clock chips to settle in order properly feed clock/reference into the subsequent stages.  We will look more closely at the enclosed SPI timing plots. --RJH

  • 0 in reply to RJ Hopper
    Prodigy 170 points

    Hi Hopper,

    Thanks. However, I dump out the ADC12DJxx00 GUI timing order out of FT4232, just like this:

    LMK04828(~1.94s)

    wait(~1.356s)

    LMX2582(~1.03s)

    wait(~0.01s)

    LMK04828(~0.13s)

    wait(~0.89s)

    ADC3200(~0.18s)

    Total length: ~5.6s (SPI Clock: 3.125MHz)

    So I will try to add some interval between the configuration of LMK/LMX/ADC. Trying to emulate closely to this situation.

  • 0 in reply to Joseph Xu
    TI__Mastermind 20541 points

    Hi Joseph,

    For the ADC register writes in the sequence you have shown you should either add a 200ms delay after you reset the device. After device reset you will have wait for some time to load the fuse register to load or you can check the status of 0x270 register and wait until to read 1 to proceed to next step.

    ADC12DJxx00
    0x0000 0xB0 // Do soft reset

    0x0270　 　Read //poll bit 0 of this register and wait to read 1. ( This will ensure all the fuse value have been loaded) or add 200mS of delay
    0x0200 0x00 // Clear JESD_EN (always before CAL_EN)
    0x0061 0x00 // Clear CAL_EN (always after JESD_EN)
    0x0201 0x03 // Set JMODE3
    0x0202 0x13 // Set KM1=19 so K=20
    0x0204 0x06 // Use TMSTP input, offset binary data, scrambler disabled
    0x0205 0x03 // Set PRBS23 Test
    0x0023 0x01 // Enable ADC Test
    0x0213 0x07 // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples
    0x0048 0x03 // Set serializer pre-emphasis to 3
    0x0061 0x01 // Set CAL_EN (always before JESD_EN)
    0x0200 0x01 // Set JESD_EN (always after CAL_EN)
    0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine
    0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Prodigy 170 points

    Hi Neeraj,

    Thanks for the reply. Now that makes a sense. I reviewed the SPI timing out of the ADC12DJxx00 GUI:

    Time (s)    ,    Data
    5.382238    ,    h0000B0
    5.4049949    ,    h020000
    5.4199003    ,    h006100
    5.4364383    ,    h020103
    5.4528463    ,    h020203
    5.4687863    ,    h020401
    5.4853078    ,    h021307
    5.4999221    ,    h004803
    5.5181216    ,    h006101
    5.5321706    ,    h020001
    5.547874    ,    h006C00
    5.5643189    ,    h006C01

    I found after resetting the device, next SPI transaction occured about 0.02s(20ms) later, while my FPGA SPI transaction interval is 1ms. I'll enlarge this interval and also add 200ms delay after reset. Let's see what will happen.

    Regards

    Joseph

  • 0 in reply to Neeraj Gill
    Prodigy 170 points

    Hi Neeraj,

    I've tried your method. No link issue still exists.

    I added 200ms delay after soft reset, and I can get 0x01 reading from 0x0270.

    Then I tried setting the interval of SPI from 1ms up to 25ms, and I can also get 0x01 from reading 0x0270.

    The following is the SPI transaction log:

    Time [s],             Analyzer Name,    Decoded Protocol Result
    3.703840520000000,    SPI,            MOSI: 0x0000B0;  MISO: 0x000000
    3.728862960000000,    SPI,            MOSI: 0x827000;  MISO: 0x000001
    3.753885400000000,    SPI,            MOSI: 0x020000;  MISO: 0x000000
    3.778907840000000,    SPI,            MOSI: 0x006100;  MISO: 0x000000
    3.803930280000000,    SPI,            MOSI: 0x020103;  MISO: 0x000000
    3.828952720000000,    SPI,            MOSI: 0x020213;  MISO: 0x000000
    3.853975200000000,    SPI,            MOSI: 0x020402;  MISO: 0x000000
    3.878997640000000,    SPI,            MOSI: 0x021307;  MISO: 0x000000
    3.904020080000000,    SPI,            MOSI: 0x004803;  MISO: 0x000000
    3.929042520000000,    SPI,            MOSI: 0x006101;  MISO: 0x000000
    3.954064960000000,    SPI,            MOSI: 0x020001;  MISO: 0x000000
    3.979087400000000,    SPI,            MOSI: 0x006C00;  MISO: 0x000000
    4.004109840000000,    SPI,            MOSI: 0x006C01;  MISO: 0x000000
    4.029132280000000,    SPI,            MOSI: 0x020000;  MISO: 0x000000
    4.054154720000000,    SPI,            MOSI: 0x820000;  MISO: 0x000000
    4.079177160000000,    SPI,            MOSI: 0x020503;  MISO: 0x000000
    4.104199600000000,    SPI,            MOSI: 0x820503;  MISO: 0x000003
    4.129222040000000,    SPI,            MOSI: 0x002301;  MISO: 0x000000
    4.154244480000000,    SPI,            MOSI: 0x802301;  MISO: 0x000001
    4.179266920000000,    SPI,            MOSI: 0x020001;  MISO: 0x000000
    4.204289360000000,    SPI,            MOSI: 0x820001;  MISO: 0x000001
    4.229311840000000,    SPI,            MOSI: 0x006C00;  MISO: 0x000000
    4.254334280000000,    SPI,            MOSI: 0x806C00;  MISO: 0x000000
    4.279356720000000,    SPI,            MOSI: 0x006C01;  MISO: 0x000000
    4.304379160000000,    SPI,            MOSI: 0x806C01;  MISO: 0x000001

    It's weird that I want to run a PRBS7/15/23 test, the DevClk is 3.2GHz, according to JMODE3 the bitrate is 6.4Gbps，but I can only get some unstable link @3.198Gbps.

    Do you have any suggestions? Thanks.

    Regards

    Joseph

  • 0 in reply to Neeraj Gill
    Prodigy 170 points

    Hi Neeraj,

    After trying several times, I can get samples. I just using the original cfg file inside the GUI folder:

    ADC12DJxx00
    0x0000 0xB0 // Do soft reset
    0x0200 0x00 // Clear JESD_EN (always before CAL_EN)
    0x0061 0x00 // Clear CAL_EN (always after JESD_EN)
    0x0201 0x03 // Set JMODE3
    0x0202 0x13 // Set KM1=19 so K=20
    0x0204 0x02 // Use SYNC_SE input, offset binary data, scrambler disabled
    0x0213 0x07 // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples
    0x0048 0x03 // Set serializer pre-emphasis to 3
    0x0061 0x01 // Set CAL_EN (always before JESD_EN)
    0x0200 0x01 // Set JESD_EN (always after CAL_EN)
    0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine
    0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration

    So my PRBS23 test config file seems having a problem.

    My further question is how to ongoing the other test mode based on the original config file?

    Regards

    Joseph

  • 0 in reply to Joseph Xu
    TI__Mastermind 20541 points

    Here are the register writes.

    ADC12DJxx00
    0x0000 0xB0 // Do soft reset

    Add a 100msecond of delay.
    0x0200 0x00 // Clear JESD_EN (always before CAL_EN)
    0x0061 0x00 // Clear CAL_EN (always after JESD_EN)
    0x0201 0x03 // Set JMODE3
    0x0202 0x13 // Set KM1=19 so K=20
    0x0204 0x02 // Use SYNC_SE input, offset binary data, scrambler disabled

    0x205 0x03  // Enable PRBS23 test pattern
    0x0213 0x07 // Enable overrange, set overrange holdoff to max period 8*2^7 = 1024 samples
    0x0048 0x03 // Set serializer pre-emphasis to 3
    0x0061 0x01 // Set CAL_EN (always before JESD_EN)
    0x0200 0x01 // Set JESD_EN (always after CAL_EN)
    0x006C 0x00 // Set CAL_SOFT_TRIG low to reset calibration state machine
    0x006C 0x01 // Set CAL_SOFT_TRIG high to enable calibration

    Regards,

    Neeraj