ADS4149: Noise Figure drift depending on the mounting process.

User,

We have not come across customer issues like this before. We are looking into this. This part has an exposed thermal pad on the bottom. Could your issue be with this pad not being soldered properly to the PCB? Is your input AC or DC coupled to the ADC? 

Regards,

Jim

Hello Jim,

It could be, but the soldering process is exactly the same and in 80 TR modules ADCs work slightly diffrent. Roughly speaking, we have a 40% working fine, 40% working not so well and 20% in a middle point not good not bad. Our PCB has this exposed thermal pad with void vias hole (not filled) and one of our worries is the reflow of solder paste. Could be that a critical point?

It could be a problem of linearity? I mean, since NF is measured with the Y factor method (measuring a low noise floor and a high noise floor), maybe gain drift between the low noise floor and the high noise floor can be different among ADCs to explind this drift performance in NF.

Regarding to the AC coupling, we use set-up of Figure 117 of  ADS4149 datasheet "Drive Circuit with High Bandwidth (for High Input Frequencies)". So, our input is AC coupled and differencially transformed after.

Best Regards,

User,

How warm is this device getting? The part has many GND pins and the solder pad is mostly used for removing heat. If it is not getting that warm, how it is mounted probably is not the cause of this issue. 

Are you using HIGH PERF MODE1? This mode improves aperture jitter of ADC by making input clock buffer stronger (by increasing its current by ~3 to 5 mA).

The impact is mainly on high input signal frequencies where jitter noise dominates overall SNR of ADC.

For examples, you may see about 1 to 1.5dB improvement in SNR at -1dBFS  with a 230MHz IF sampling at 250MSPS.

Impact on sampling frequencies: If the rise and fall time of clock signal is same across sampling frequencies, impact of this MODE should not depend on clock sampling rate.

However, it is seen, especially in case of sine wave clock, that rise/fall time of clock signal degrade for lower sampling rates which in-turn degrade the aperture jitter of ADC’s clock buffer.

Since this MODE makes the input clock buffer stronger, its impact is more visible at lower sampling rates.

In summary, this MODE is the most helpful for high IF/Low FS combination, and its predominant impact is on SNR, may improve HD2 slightly (1dB or 2) as well.

Power supply noise will also reduce SNR performance. Is there a chance you may have noise on your power?

I am waiting to here back from the design team regarding your other questions. 

Regards,

Jim

It is not easy to measure temperatures in ADCs or a near area to de ADCs, but we have changed from 0ºC to 50ºC the enviromental temperature in a climate chamber and we can see every TR module increase arround 0.4dB the NF respect to the 0ºC temperature. It is curious, because this drift is quite similar among TRMs (0.4dB) and the difference due to mounting process (or at least this is what we suppose) keep being the same with any themperature configuration of the chamber. Consequently, I don't think the temperature of this pad is affecting. We are also changing the disipation interface with the exposed pad of the ADC and we get similar results in good and bad boards.

We had configured HIGH PERFORMACE MODES (1, 2, both...) and we don't see any difference in NF measurements. We use differential square signal CLOCK, so I suppose phase noise (or jitter) of the clock is not affecting in NF. In addition, we measure NF in our bandwith, so any noise addition must be in that bandwith to get worse the performance.

We have been able to compare power supply in a couple of TRM (one with good NF and other with worse NF) and we find no difference between them.The VCM ADC provides is exactly the same in both modules (measuring with multimeter, oscilloscope and spectrum analyzer).

As I think this issue can be a problem of linearity, could you provide me more measurements of the integral nonlinearity (Figure 98 in ADS4149 datasheet) for different ADS4149 serial numbers? I'm interested in test linearity drift among ADCs and if you can give me that info it is greatly appreciated.

Thank you for your effort Jim,

Best,

Diego,

Diego,

I have requested for this data from the design team but not sure they have anything to offer as this is an old device.

Regards,

Jim 

Thank you very much Jim.

Regards,

Diego

Diego,

It appears we do not have this data.

Regards,

Jim

Hello Jim,

It's a pity because I think it could give us some important info. Could you tell me how that linearity measurement is done (with a little more details than the datsheet if it is possible) in order to repeat with some ADCs in our laboratory?

Thank you beforehand,

Regards,

Diego

Diego,

Please find the attached data of MAX and MIN INL, that was downloaded data from production.

Values are in LSB and plotted as BOX plot. I will see what I can find out about the testing methodology. 

Regards,

Jim

ADS4149_INL.pdf