ADS1220: About ACTUAL CONVERSION TIME

Hi Hide,

The tclk period is based on the internal oscillator frequency (tclk = 1/fclk) when the internal oscillator is used, or by the external clock frequency when an external clock is used.  So the number of clock cycles are used instead of a specific time as the clock frequency can vary depending on the use case.

The tclk for the internal oscillator is designed around 4.096MHz clock.  This is discussed at the top of the section in 8.3.5 of the ADS1220 datasheet.  So the tclk period is 1/4.096MHz.  However the internal oscillator time can vary as much as  +/-2% which is directly proportional to the total time of conversion.

So part of the clock confusion I think is the ADS1220 is a Delta-Sigma oversampling device and the conversion clock does not relate to the SCLK frequency, but rather the modulator clock (256 kHz).  So for Q1 the figure 63 does not apply with respect to the total conversion timing.  You need to use Table 11 conversion timing.  If the internal oscillator is used you will also need to consider the oscillator startup time of 50us to be added to the Table 11 timing.

Q2 timing for the length of the conversion period would typically be 50us (oscillator startup time for SS mode) + (204850 tclk periods) * (1/4.096MHz).

Best regards,

Bob B