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THS8200 1920x1080i 50Hz problem

wen kui
Prodigy 30 points

Other Parts Discussed in Thread: THS8200

hi

is there any example of  register setup about 1920x1080i 50Hz  video standard.

I find register 0x26 (dtg_spec_b)   is limited to 255  which cannot cover 50Hz systerm.

I search the forum but don't find the answer.

my register setup is as below:

 0x03,// 0x19   
 0x00,// 0x1A  tst_cntl
 0x00,// 0x1B  tst_ramp_cntl
 0x0B, //0x1C  dman_cntl
 0x00 ,//0x1D  dtg_y_sync1 setup tri-level sync
 0x49 ,//0x1E  dtg_y_sync2
 0xB6 ,//0x1F  dtg_y_sync3
 0x00 ,//0x20  dtg_cbcr_sync1
 0x00 ,//0x21  dtg_cbcr_sync2
 0x00 ,//0x22  dtg_cbcr_sync3
 0x23 ,//0x23  dtg_y_sync_upper
 0x2A ,//0x24  dtg_cbcr_sync_upper
 0x2C ,//0x25  dtg_spec_a use spec registers to set up horizontal timing
 0xFF ,//0x26  dtg_spec_b    1080i50hz
 0x2C ,//0x27  dtg_spec_c
 0x84 ,//0x28  dtg_spec_d
 0x00 ,//0x29
 0xC0 ,//0x2A  dtg_spec_e
 0x00 ,//0x2B  dtg_spec_h_msb
 0x00 ,//0x2C  dtg_spec_h_lsb
 0x00, //0x2D
 0x00, //0x2E
 0x34 ,//0x2F  dtg_spec_k_lsb 1080i50hz
 0x01 ,//0x30  dtg_spec_k_msb 1080i50hz
 0x00 ,//0x31  
 0x58 ,//0x32  dtg_speg_g_lsb
 0x00 ,//0x33  dtg_speg_g_msb
 0x0A ,//0x34  dtg_total_pixel_msb   1080i50hz
 0x50 ,//0x35  dtg_total_pixel_lsb   1080i50hz
 0x00 ,//0x36  dtg_linecnt_msb
 0x01 ,//0x37  dtg_linecnt_lsb
 0x81 ,//0x38  dtg_mode select 1080i mode (defines vertical structure the video frame)
 0x42 ,//0x39  dtg_frame_field_msb 465h =1125 lines per frame
 0x65 ,//0x3A  dtg_frame_size_lsb 233h = 563 lines per field
 0x33 ,//0x3B  dtg_field_size_lsb

  • 0
    TI__Genius 16810 points

    Hi Wen,

    Below are THS8200 settings that can be used for 1080i50Hz.  This setup is for 20-bit input format with embedded syncs.  You are correct that dtg_spec_b is limited to 255 and cannot cover the entire 1080i50 front  porch.  This setting define the interval where the THS8200 forces the DAC output to blank/black level.  1080i50 can stil be supported, but the THS8200 cannot override the input data and force a blank/black level outside this range.  This should not be an issue if the YCbCr data is SMPTE 274M compliant and is at black level during blanking.

    // THS8200 1080i50Hz 20-bit YCbCr with embedded syncs

                                                   REG,DATA
    WR_REG,THS8200,0x01,0x03,0x01 // chip_ctl           
    //CSC setup not required if not used     
    WR_REG,THS8200,0x01,0x19,0x03 // csc_offset3  - CSC bypassed
    WR_REG,THS8200,0x01,0x1C,0x53 // dman_cntl  - 20 bit input format
         
    // composite sync amplitude control
    WR_REG,THS8200,0x01,0x1D,0x00 // dtg_y_sync1        
    WR_REG,THS8200,0x01,0x1E,0x49 // dtg_y_sync2        
    WR_REG,THS8200,0x01,0x1F,0xB6 // dtg_y_sync3        
    WR_REG,THS8200,0x01,0x20,0x00 // dtg_cbcr_sync1     
    WR_REG,THS8200,0x01,0x21,0x00 // dtg_cbcr_sync2     
    WR_REG,THS8200,0x01,0x22,0x00 // dtg_cbcr_sync3     
    WR_REG,THS8200,0x01,0x23,0x23 // dtg_y_sync_upper   
    WR_REG,THS8200,0x01,0x24,0x2A // dtg_cbcr_sync_upper
    // horizontal timing setup
    WR_REG,THS8200,0x01,0x25,0x2C // dtg_spec_a         
    WR_REG,THS8200,0x01,0x26,0xFF // dtg_spec_b   maxed out      
    WR_REG,THS8200,0x01,0x27,0x2C // dtg_spec_c         
    WR_REG,THS8200,0x01,0x28,0x84 // dtg_spec_d         
    WR_REG,THS8200,0x01,0x29,0x00 // dtg_spec_d1        
    WR_REG,THS8200,0x01,0x2A,0xC0 // dtg_spec_e         
    WR_REG,THS8200,0x01,0x2B,0x00 // dtg_spec_h_msb     
    WR_REG,THS8200,0x01,0x2C,0x00 // dtg_spec_h_lsb     
    WR_REG,THS8200,0x01,0x2D,0x00 // dtg_spec_i_msb     
    WR_REG,THS8200,0x01,0x2E,0x00 // dtg_spec_i_lsb     
    WR_REG,THS8200,0x01,0x2F,0x34 // dtg_spec_k_lsb     
    WR_REG,THS8200,0x01,0x30,0x01 // dtg_spec_k_msb     
    WR_REG,THS8200,0x01,0x31,0x00 // dtg_spec_k1        
    WR_REG,THS8200,0x01,0x32,0x58 // dtg_speg_g_lsb     
    WR_REG,THS8200,0x01,0x33,0x00 // dtg_speg_g_msb     
    WR_REG,THS8200,0x01,0x34,0x0A // dtg_total_pixel_msb 2640
    WR_REG,THS8200,0x01,0x35,0x50 // dtg_total_pixel_lsb
    WR_REG,THS8200,0x01,0x36,0x80 // dtg_linecnt_msb    
    WR_REG,THS8200,0x01,0x37,0x01 // dtg_linecnt_lsb
    WR_REG,THS8200,0x01,0x38,0x81 // dtg_mode   - 1080i       
    WR_REG,THS8200,0x01,0x39,0x42 // dtg_frame_field_msb
    WR_REG,THS8200,0x01,0x3A,0x65 // dtg_frame_size_lsb 
    WR_REG,THS8200,0x01,0x3B,0x33 // dtg_field_size_lsb
    WR_REG,THS8200,0x01,0x41,0x40 // csm_clip_gy_low    
    WR_REG,THS8200,0x01,0x42,0x40 // csm_clip_bcb_low   
    WR_REG,THS8200,0x01,0x43,0x40 // csm_clip_rcr_low   
    WR_REG,THS8200,0x01,0x44,0x53 // csm_clip_gy_high   
    WR_REG,THS8200,0x01,0x45,0x3F // csm_clip_bcb_high  
    WR_REG,THS8200,0x01,0x46,0x3F // csm_clip_rcr_high  
    WR_REG,THS8200,0x01,0x47,0x40 // csm_shift_gy       
    WR_REG,THS8200,0x01,0x48,0x40 // csm_shift_bcb      
    WR_REG,THS8200,0x01,0x49,0x40 // csm_shift_rcr      
    WR_REG,THS8200,0x01,0x4A,0xFC // csm_mult_gy_msb    
    WR_REG,THS8200,0x01,0x4B,0x44 // csm_mult_bcb_rcr_msb
    WR_REG,THS8200,0x01,0x4C,0xAC // csm_mult_gy_lsb    
    WR_REG,THS8200,0x01,0x4D,0x91 // csm_mult_bcb_lsb   
    WR_REG,THS8200,0x01,0x4E,0x91 // csm_mult_rcr_lsb   
    WR_REG,THS8200,0x01,0x4F,0xFF // csm_mode           
    // discrete output sync control      
    WR_REG,THS8200,0x01,0x70,0x2C // dtg_hlength_lsb    
    WR_REG,THS8200,0x01,0x71,0x0A // dtg_hdly_msb       
    WR_REG,THS8200,0x01,0x72,0x4F // dtg_hdly_lsb       
    WR_REG,THS8200,0x01,0x73,0x06 // dtg_vlength_lsb    
    WR_REG,THS8200,0x01,0x74,0x00 // dtg_vdly_msb       
    WR_REG,THS8200,0x01,0x75,0x01 // dtg_vdly_lsb       
    WR_REG,THS8200,0x01,0x76,0x00 // dtg_vlength2_lsb   
    WR_REG,THS8200,0x01,0x77,0x00 // dtg_vdly2_msb      
    WR_REG,THS8200,0x01,0x78,0x00 // dtg_vdly2_lsb 
    // discrete input sync  control - use to align picture  
    WR_REG,THS8200,0x01,0x79,0x02 // dtg_hs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7A,0x32 // dtg_hs_in_dly_lsb  - adjust horizontal
    WR_REG,THS8200,0x01,0x7B,0x00 // dtg_vs_in_dly_msb  
    WR_REG,THS8200,0x01,0x7C,0x02 // dtg_vs_in_dly_lsb  - adjust vertical
    WR_REG,THS8200,0x01,0x82,0x3B // pol_cntl, embed syncs enabled          

  • 0 in reply to Larry Taylor
    Prodigy 30 points

    Hi Larry

    Thank you very much,now it works well 。

    I just find the picture a little right shift. 

    Which register I can adjust to modify this problem?

    Thanks

    Wen