TLA2518: t_quiet time between sclk falling edge and cs rising edge

Yawi Miki

Part Number: TLA2518

Hi,

I am using TLA2518 chip. there is quiet time mentioned in the timing graph but I could not find any values regarding to that in the datasheet. are there any timing constrain in between final sclk falling edge and cs rising edge?

Thank you,

over 5 years ago

0 RahulVK over 5 years ago

TI__Expert 3805 points

Hi Yawi Miki,

The quiet acquisition time is 10ns. It is specified as t_{QT_ACQ} in the timing requirements table. I have made a note to update the nomenclature in the interface waveform.

0 Yawi Miki over 5 years ago in reply to RahulVK

Prodigy 140 points

Hi Rahul,

Thank you for the quick reply, is this 10 ns maximum or minimum time? if this is the minimum, what would be the maximum value?

Kind regards,

Yawi

0 RahulVK over 5 years ago in reply to Yawi Miki

TI__Expert 3805 points

Hi Yawi Miki,

The quiet acquisition time is a minimum spec. There is no upper limit on the duration between the last SCLK edge and CS rising edge.

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TLA2518: t_quiet time between sclk falling edge and cs rising edge