ADS1278 in modulator mode

Hi Ratesh,

You can enable modulator mode by setting the external FORMAT [2:0] bits to 110. This is completed using hardware as there are not internal registers that you can access. So you will need to set the FORMAT pins accordingly. The MODE [1:0] pins are used to set the modulator output clock.I would also make sure you have your FPGA configured correctly so the pin you are using for SCLK on the FPGA is an input. Make sure that the FPGA is not pulling the SCLK line low or high.

If you use the modulator mode, the internal digital filter is bypassed and the modulator output appears on DOUT. If you use the ADC in normal mode, the ADC uses a coefficient based FIR filter for filtering. You should know that this filter creates a 76 cycle latency to have fully settled data when stepping a DC signal. Could you elaborate a little more on what filter specifications you are concerned with?

Regards,

Tony Calabria

Dear Tony,

Thanks for your kind reply. I have already done the above configurations as I mentioned in the last post. All these configurations are provided in the Data Sheet on page no 35. I also made the FPGA input as NC, but still I am not getting the SCLK. It is showing only the high level (3.3 V level). Apart from that what other things I can do to receive the SCLK Clock.

Regarding the question no 2, I just want to know about the inbuilt filter specifications. What are the stopband frequency, passband frequency, filter gain/loss, no of taps etc so that I can replicate the same filter in my FPGA.

Thanks once again.

Regards

Ritesh Sharma

Hi Ritesh,

The last thing to check is to make sure that you have a master clock (fclk) applied to the device in order for the modulator to sample properly. Other than that, do you mind posting a schematic so I can see your other connections to see if anything stands out as incorrect?

Regards,

Tony

Dear Tony,

I have applied the master clock of 4MHz to the devices and it is also verified that signal is going to the ADCs. Somehow I'll try to manage the schematic but it'll take little time.

One more important detail is that I am having three(3) ADS1278 devices on my card.

Do you have any clue about the FIR filter design inside the ADS1278 and also what are the performance number (ENOB, INL, DNL etc.) of the ADC.

Thanks and regards

Ritesh

Hi Ritesh,

We generally are unable to give out our filter details without an NDA as it is part of the ADS1278's design. You can think of it as a FIR filter with 78 tap points. Aside from that, you can estimate the linearity (INL) using the rule of thumb that 1ppm linearity = -120dB THD and then will degrade 6dB with each ppm of linearity. The INL estimate is taken using line of best fit method. For example - 

-120dB THD = 1ppm INL

-114dB THD = 2ppm INL

-108dB THD = 4ppm INL

-102dB THD = 8ppm INL

-96dB THD = 16 ppm INL

Notice that the INL will double with each 6 dB increment.The FIR filter behavior and roll off is shown in Figures 58 and 59 of the data sheet. We spec -108dB THD in the data sheet which would come out to about 4ppm INL.

Lastly, ENOB can be calculated from (SINAD-1.76)/6.02. Since we do not list SINAD, you can use SNR as an estimate of the SINAD. Doing so gives me about 17.31bits ENOB theoretically using 106dB SNR as the SINAD for high resolution mode. You would probably expect the SNR to be maybe five dBs higher than the SINAD, so the ENOB would be slightly less than what is calculated using SNR. I used the ADS1278EVM in the lab with ADCPro and saw the ENOB was slightly higher than 16.5 bits.

Regards,

Tony Calabria

Dear Tony,

Thanks for your cooperation.

I have resolved the modulator clock issue, and grabbed the modulator output successfully.

Now as per your last reply you have achived ENOB of slightly higher than 16.5 bits. Can you just give a brief driscription of the setup (i.e. Analog I/P Source (Make), Power supply etc.) so that we can also replicate the same one in our lab.

We have also tried on your EVM module only but didn't received even upto 16 bits.

If it is 24-bits ADC then why it is not showing the performance 18-19 bits or better than that?

Kindly reply in this regards.

Ritesh Sharma