Part Number: DAC3161
Folks,
We've designed the TI DAC3161 into a PCB and we are clocking the device at 500 MHz; i.e. the maximum specified sample rate. My question is this: What is the maximum skew of the DAC3161 between the twelve digital input data bits with respect to the input data clock? I searched the datasheet, and the word "skew" is nowhere to be found.
I realize that the DAC3161 has the ability to shift the set-up and hold times by writing to registers as described on pages 16 & 17 of the datasheet, but that is not my issue. I need to know how much the DAC data bits are skewed on the DAC3161 itself so that I can determine how much additional skew the part will tolerate due to trace length mismatches on the PCB and still function properly at 500 MSPS. Our board is currently in PCB artwork with an aggressive schedule, so I would appreciate a speedy reply to this question. Sincerely, - Mike Amirault
