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ADS6125: Operation at DRVDD < 2.2V

Jejomar Ildefonso
Genius 9490 points
Part Number: ADS6125

Hi Team,

Posting on behalf of our customer. They intend to operate ADS6125 in parallel CMOS but the datasheet apparently lacks information on the reason the external clock is preferred to use over CLKOUT at DRVDD < 2.2V. Currently they are using CLKOUT and operating at DRVDD=1.8V. They've encountered some noises which is quite expected to some extent but they'd like to know the main factors that contributes these noises.

Are the rising edges not fast enough being a concern? Too low voltage?

Would really appreciate your inputs. Thanks!


Kind Regards,

Jejomar




  • 0
    TI__Mastermind 18095 points

    Jejomar:

    For lower DRVDD the drive strength of the CMOS buffers is lower.  This translates to slower (i.e less sharp) transitions which become susceptible to noise.  The external clock is recommended to allow more flexibility in maintaining sample/hold times.  "Weaker buffer" is also susceptible to impact due to traces and capacitive loading.

    --RJH