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DAC80508EVM: Can't get DAC to output, SDO pin is acting unexpectedly

Part Number: DAC80508EVM
Other Parts Discussed in Thread: USB2ANY

First off, I am not using USB2ANY to control the eval board, I don't have the cable. I am using an FPGA controller (CMOD A7) to connect directly to the CS, SCLK, SDI & SDO pins. I have attached a couple of oscilloscope snapshots of my timing, I apologize for the quality of the pictures, as our oscilloscope doesn't have screen capture. The orange/yellow curve is SCLK, the white curve is SDI, the blue curve is CS, and the green curve is SDO.

The following image shows me trying to write the value 0x8fff to DAC 4, and the second one shows a single bit going high to show what side of SCLK I am writing on. Overall, I'm writing 0x0b 8f ff.

Next, I tried reading the DEVICE ID register, so I sent 0x81 00 00 to the DAC, however what I got back was not what I had expected, as you can see in the next picture. I also tried to read other registers, but the SDO pin had the same value no matter which address I entered.

I ended up leaving the SDO trace on the oscilloscope and tried to write to the DAC again, and it was jittering around two or three different values, which was surprising. I have attached one such state.

From my understanding of the default values, even if I don't initialize registers myself, I should be able to write to a DAC, is this correct? Currently, I'm guessing that I'm not writing to any of the registers, but I am getting some kind of response from the SDO pin, so I'm not sure about that.

If you see any obvious timing problems, or things I am writing incorrectly, please let me know. I am powering both VDD and VIO with 3.3V from the FPGA. If you need any additional information from me, or want me to try something out, feel free to tell me.

Thank you!

  • Hi Mathew,

    It is important to understand that a readback function requires two commands: first, as read command is issued.  Then, another SPI packet must be sent, during the next 24 clock periods the data will be clocked out on SDO.

    The second command can be a NOP command (all 0s) or the next write command.

    Please verify if you can use the read command now to read the DEVICE ID register.



  • Paul,

    Thanks for the reply. I am continuously sending the command 0x810000, which should be the command to read the DEVICE ID register. From my understanding, if I keep sending this command continuously, then the next cycle SDO should return the value of the register. This is what I did in the 3rd picture above, where every command sent is the read command, therefore every time cs goes low it should return the value of the register, except for the first time. Is this correct?



  • That is correct.  Sending the command multiple times would repeat the read.

  • So that's what I did in the third picture, and the response I got back from the DAC is 0x300003, which is the green trace in the picture.

  • The third image shows an issue with the most significant bit.  The bit does not seem to be held high during the falling edge of the clock.  Can you try to resolve that?

  • I'm not sure how to resolve that, as that is the SDO pin, so the DAC is writing that to me. I noticed that too, however I ignored it as I wasn't sure what to expect from the SDO pin right after CS goes low but SCLK hasn't gone high. Do you have any ideas as to why it would be going high between those two events?

  • Well, going back and trying it again today, I am even more confused. It seems that the SDO pin waveform changes on my oscilloscope depending on what other pins I am probing, which seems quite odd to me. I am using the oscilloscope in 50 Ohm mode, however that would sitll only be 60 mA per channel, and my FPGA can output 600mA of 3.3V power, so I'm not sure why its changing. The SCLK, SDI and CS pins don't change waveform no matter what test leads I probe. Do you know why this would happen?

  • I decided to test it with a Arduino Uno I had lying around, and write a quick SPI program with it with the standard SPI library. With this, I was able to read and write as expected. I also noticed that with the 5V supply from the arduino, The DACs defaulted to outputting 2.5V. I then hooked up a switching power supply that provides 5V to the VDD and VIO pins, with nothing connected to the IO pins, and the DACs output 2.5V. I then hooked up the 3.3V power supply from the CMOD A7 to the pins, and got 0V out. This is quite confusing to me, as it should only be drawing at max 6mA, and the FPGA says it can output >250mA, so why does it default to a midpoint DAC value with a 5V supply but not a 3.3V supply?

  • Alright, so after quite a bit of testing, I believe I've figured out what the big problem is. I am now using a variable power supply to power VDD and VIO on the DAC, and the power-on-reset only occurs when I turn the voltage up to above ~3.6V. If I have the voltage around 3.6-3.8V, I can control the DACs just fine with my FPGA. However, when VDD/VIO go above about 3.8V, I can no longer control them. My logic signals are 3.3V, so they should still be above the stated 0.7*VIO, but it doesn't work. Do you know why below 3.6V the DAC doesn't turn on or work? The spec sheet says it should work down to 2.7V, so I'm somewhat confused.

    EDIT: Changed voltage values, variable power supply readout didn't match multimeter. Corrected with multimeter values.

  • Hi Mathew,

    I am concerned that using this 50Ω termination is causing a problem.  It should not be necessary for this inspection.  In your scope shots look like the logic high voltage was less than 2V.  If you are configuring your FPGA for 50-ohm termination, then the amplitude would need to be 2x the logic high voltage.

    Can you verify with the scope set to high-impedance? 

    If you are using 50 terminations on a 50Ω output, then your digital logic levels will be reduced by 50%, so your logic signals might not be as high as you expect.

    The DAC should be able to function at below 3.6V, so I am concerned something else is going on.  

    Can you also share your schematic?

  • Hi Paul,

    You were right, I was using the oscilloscope in 50 Ohm mode, and that was dropping the logic signals. Now, they work up to about 4.5V, which is about what I would expect from the spec sheet, thanks for pointing that out.

    As for the DAC not initializing the registers, when I only attach the power supply to the board, and nothing else is connected, it still only turns on at about 3.6V. I have attached a quick drawing of the setup, it's pretty basic, none of the other pins are connected (except a multimeter connected to DAC 0). If you have any ideas as to why the DAC outputs wouldn't be initializing to the midpoint value when below 3.6V, it would be greatly appreciated.

    Thanks for pointing out the 50 Ohm termination!



  • Hi,

    Going forward, I will be taking over this thread from Paul.

    Whats is the supply voltage when the DAC powers up? Is it 3.3V? For  VDD below or equal to 3.3V, we cant have reference of 2.5V, there is no headroom for the internal buffer to operate and it will be shut down, That's the reason you are not getting output.

    For that we have an internal divider for reference, you need to enable the /2 mode. As soon as you enable the div by 2, in GAIN register, you will be good to go.

    If the power supply is above 3.3V, no problems with respect to the above issues.

    Steps to follow.

    1. Power up the device.

    2. Write into GAIN register

    Please see the reference input specifications below. 

    Let me know this helps.



  • Hi,

    Any update on the issue? Do you need further help?