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ADS131M08: Master clock synchronized with spi clock.

Paulo Pecegueiro
Prodigy 120 points

Part Number: ADS131M08

Hi, I want know what the text mentioned below exactly means with:

"For optimal performance, the

modulator sampling clock must be synchronous with the serial data clock SCLK. The modulator sampling clock
is derived from the master clock which means the master clock should be synchronous with the SCLK."
(8.3.5 Clocking and Power Modes

, Pag.17)

My questions are:

What is this performance gain?

The performance gain refers to what?

How much is this performance gain between using or not using a master clock synchronized with the spi Clock?

  • 0
    TI__Guru** 101175 points

    Paolo,


    For other ADCs, we've recommended using an SCLK and master clock that are synchronized and in phase. Typically we recommend some some integer multiple of the master clock frequency to run the SCLK.

    By using a synchronized SCLK, this allows the clock edges to line up, removing any random contribution of clock edge energy during the sampling of the ADC and reference. This extra energy may show up in the FFT of the sampled output data. By using a synchronized SCLK, you remove this extra contribution.

    Typically, the difference between the two cases is small but noticeable. However, I'm not aware of any differences in performance for this device. I've sent an email to the characterization group to find out if we've specifically characterized this behavior in this device and I'll get back to you when I find out.


    Joseph Wu

  • 0 in reply to Joseph Wu
    Prodigy 120 points

    Hi Joseph, thanks for your reply. Did you get information about the performance improvement and noise reduction? I mean concrete number and data to compare. The ENOB table presented in the datasheet was made for which cases?

  • 0 in reply to Paulo Pecegueiro
    TI__Guru** 101175 points

    Paolo,

    The ENOB tables were made with the SCLK synchronous and in phase with CLKIN. I did get a comment from the characterization engineer that with the SCLK not in phase with CLKIN there may be some small signal seen in a DC measurement. He had noticed this when using the crystal oscillator with the device. He didn't give any specific numbers for the small signal.

    Another engineer noted that with the SCLK not in phase with the CLKIN, there was extra noise. In that case, he had tested different SCLK frequencies and some modest increases in noise depending not only on frequency but channel as well. For most of the frequencies of SCLK, the noise stayed about the same. However, there was a spike with SCLK at 1x and 1.5x of CLKIN with the clock not in phase. The extra noise for those peaks was about 1.6 higher than the normal noise. 

    Joseph Wu