ADS8684A: SPI timming

Hello Hiroaki,

The SCLK frequency is not determined by the sampling rate, this is the clock provided by your MCU. When your sampling rate is reduced to 50ksps, your SCLK can be still 17MHz. 

The conversion data is launched to the SDO at the rising edge of SCLK, the setup time (tSU_DOCK) is the time from SDO data available to the falling edge of SCLK which is around half of SCLK period, also your SCLK is restricted to 17Mhz, thus this 25ns is the minimum time for the setup time (tSU_DOCK). When your SCLK is slow, this time will be longer.

There is no min limit on the sampling rate.This ADC integrates a ADC driver on each channel which can handle the signal settling on sample/hold capacitors.

Regards,

Dale

Dale-san,
Thank you for your support.

I understand that the sampling rate is the CS period, not the SCLK frequency.

If the SCLK from the MCU is limited (eg up to 10MHz), can Setup time (tSU_DOCK) have more than 25nsec?
In that case, is there a setup time calculation formula?

My current design does not have a margin only with the setup time 25nsec of CLK and Dout timing from MCU.

Best Regards,
Hiroaki Yuyama

Hiroaki-san,

 The tSU_DOCK is not the timing requirement for your MCU and this is the minimum time for the ADC to setup the data on the SDO, it's specified from the SDO data available to the falling edge of SCLK which is around half of SCLK period. When your SCLK is 0MHz, the time left to the ADC to setup the signal is around (1/10M)/2=50ns which is higher than the minimum requirement and it's good enough for the ADC.

Best regards,

Dale