TSW1400EVM: Getting "Frame Clock error in Read DDR to file error" message when downloading the .rbf file generated by the quartus II demo program

Hi,

Thank you for using AFE5818EVM and TSW1400EVM.

Actually when we are running AFE5818EVM with TSW1400EVM,

we are using ADC_FIRMWARE.rbf

under: C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\1400 Details\Firmware

which will set up all the correct settings,

however using other .rbf files may not be compatible with AFE5818 device

and it may cause the error message happened.

Thank you!

Thank you for your reply.
Now we need to use TX7316EVM+AFE5818EVM+TSW1400EVM to build a simple ultrasound transceiver system. We need to use TSW1400EVM FPGA to communicate with TX7316EVM without affecting data capture, so we need to modify Verilog on the basis of quartus II project DEMO.
But now the .rbf file generated by the DEMO cannot capture the AFE5818EVM data normally, so we cannot add the communication function before solving this problem. Do you have any suggestions?

Thanks.

I mean, can you give me some hints on how I should modify the quartus II project to be compatible with AFE5818EVM, such as modifying the data length received once, the system clock or the like.