Other Parts Discussed in Thread: CC2652RB
The datasheet for the ADS129X states:
When DRDY transitions low, new conversion data are ready. The CS signal has no effect on the data ready signal. Regardless of the status of the CS signal, a rising edge on SCLK pulls DRDY high. Thus, when using multiple devices in the SPI bus, gate SCLK with CS.
Because I am using multiple SPI peripherals, I have used a SN74SUP1G98 gate for this in the past—which has many small package options—but in the spirit of minimizing components and interfacing with the CC2652RB, I'm wondering if there are any disadvantages (or hidden advantages) to giving the ADS129X it's own SPI port, given I have enough GPIO? The primary advantages I see are:
- I can remove the gate hardware since the SCLK will be dedicated to the ADS129X.
- Possibly some advantages to having my SPI NAND flash on different pins?
- Use different protocols without updating them.
- Dedicated ports for "reading" and "writing".
My only concern would be if I begin using the sensor controller, would I be able to, say, read data from one SPI port and write it to another SPI port?