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ADS1298: Using separate SPI port instead of external gate on SCLK with ~CS?

Part Number: ADS1298
Other Parts Discussed in Thread: CC2652RB

The datasheet for the ADS129X states:

When DRDY transitions low, new conversion data are ready. The CS signal has no effect on the data ready signal. Regardless of the status of the CS signal, a rising edge on SCLK pulls DRDY high. Thus, when using multiple devices in the SPI bus, gate SCLK with CS.

Because I am using multiple SPI peripherals, I have used a SN74SUP1G98 gate for this in the past—which has many small package options—but in the spirit of minimizing components and interfacing with the CC2652RB, I'm wondering if there are any disadvantages (or hidden advantages) to giving the ADS129X it's own SPI port, given I have enough GPIO? The primary advantages I see are:

  1. I can remove the gate hardware since the SCLK will be dedicated to the ADS129X. 
  2. Possibly some advantages to having my SPI NAND flash on different pins?
    1. Use different protocols without updating them.
    2. Dedicated ports for "reading" and "writing".

My only concern would be if I begin using the sensor controller, would I be able to, say, read data from one SPI port and write it to another SPI port?

  • Hi Matt,

    Having a dedicated SPI controller though not mandatory would certainly help.

    I am not exactly following your comment on dedicated port for reading and writing. Are you referring to reading from the device ADS129x and writing to flash memory?

    I may not be able to comment on the capability of the sensor controller having separate ports for reading or writing. But I do not see a reason why it would not be possible since the sensor controller are meant to interface to multiple sensors.

  • Thanks, Praveen. It seems as though the architecture is flexible and fast enough to switch between SPI protocols if I needed to at the speeds I'm operating at (slow), but I'm just thinking about the CC2560RB as a 'bridge' between the ADS129X and NAND flash, at least for my standard data logging mode. Whether or not dedicated pins have advantages from a threading/multitasking perspective is a bit beside my original question, since I would prefer the ADS129X DRDY pin to not be reset from another peripheral's clock signal (even though DRDY will be on a HWI).