TSW14DL3200EVM: Request for FPGA Reference Design

Alec Huang

Part Number: TSW14DL3200EVM
Other Parts Discussed in Thread: ADC12DL3200, , ADC12DL3200EVM

Hi,

We are planning to use ADC12DL3200 paired with TSW14DL3200EVM in our project. Could you provide some kind of FPGA reference design / source code (preferably on Vivado)?

Best Regards,

Alec

over 5 years ago

0 jim s over 5 years ago

TI__Guru* 91947 points

Alec,

Reference design source code for this can be downloaded from the link below.

Regards,

Jim

txn.box.com/.../qh16i3kd264ie3pt43oz6v300ktoaxyr

0 Alec Huang over 5 years ago in reply to jim s

Prodigy 105 points

Hi Jim,

Thanks for the reference design. It really helps a lot!

There's one more thing. Is there any simulation design that you can share with us? It would be helpful if we could know the whole system working in practice.

Best Regards,

Alec

0 jim s over 5 years ago in reply to Alec Huang

TI__Guru* 91947 points

Alec,

Can you explain in more detail exactly what type of simulation you are looking for? Is this VHDL/Verilog type simulation? If so, I can check with the design team.

You can download the EVM User's Guide from the ADC12DL3200EVM product folder on the TI website for an example of a working system.

Regards,

Jim

0 Alec Huang over 5 years ago in reply to jim s

Prodigy 105 points

Hi Jim,

We would like to have VHDL/Verilog simulation. Thank you!

Best Regards,

Alec

0 jim s over 5 years ago in reply to Alec Huang

TI__Guru* 91947 points

Alec,

IBIS models are not yet available but we can provide simulation data.

We have raw FFTs, HDx vs. input freq sweeps for different modes and IMD3 plots. Please let us know if this is what you are interested in and we can send this data We also have some initial measurement plots from our test bench available.

Regards,

Jim

0 jim s over 5 years ago in reply to jim s

TI__Guru* 91947 points

Alec,

Please ignore the last post as I confused this request with another device. We do have IBIS models available under the ADC12DL3200 product folder on the TI website.

Regards,

Jim

0 Alec Huang over 5 years ago in reply to jim s

Prodigy 105 points

Hi Jim,

Could you send me the files you mentioned above? (FFTs, input frequency sweep etc.)

Also, is it possible for you to provide the test bench file? We need it to assess the latency throughout and within the design.

Best Regards,

Alec

0 jim s over 5 years ago in reply to Alec Huang

TI__Guru* 91947 points

Alec,

You should be able to find the FFT and some input frequency sweep data for the ADC12DL3200 in the data sheet. I am looking to see if we have any test bench files available.

We did some early testing to attempt to measure the overall latency of a link between the ADC and a Xilinx FPGA. The data from this test is attached.

Regards,

Jim

ADC latency measurement.docx

0 Alec Huang over 4 years ago in reply to jim s

Prodigy 105 points

Hi Jim,

We encountered a problem relating failed routes during implementation stage. Could you help us with this problem? We are running the reference design you provided on Vivado 2019.1.

Best Regard,

Alec

0 jim s over 4 years ago in reply to Alec Huang

TI__Guru* 91947 points

Alec,

Are you using this firmware on the TSW14DL3200EVM or another platform? When you move across FPGAs, things like FIFOs, BRAMs, etc transition seamlessly. However, specialized IP like the HSSIO (the LVDS I/O) and the JESD transceivers have very rigid requirements. If you are using a different FPGA, you should use the reference design purely as a reference and customize the LVDS IP to match the FPGA of choice.

Regards,

Jim

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TSW14DL3200EVM: Request for FPGA Reference Design