Part Number: ADC12DJ5200RF
Other Parts Discussed in Thread: LMK00304, LMX2594, LMK04828, LMK04832, DS90LV032A
Hi,
I am designing a multichannel receiver board with 4 nos of adc12dj5200RF. Kindly let me know if there is any reference design for the same.
Regards,
Pratiksha
Hi,
Thanks for the quick reply.
Kindly clarify the following queries.
1. Is it mandatory to sync ADC regulators to an external clock (Referring to Page 11/13 of ADC12DJ5200EVM SCHEMATIC?)
2. Kindly review the clock scheme attached herewith and let me know if any corrections are required.
Note: There is no provision for external RF clock. However, external RF reference will be available in the system.
Proposed clock scheme:
1. LMK00304 receives an external clock reference and an on-board reference. Based on the select control, it selects either internal or external reference and generates two copies of the input signal.
a. One copy is given to LMK00304, which generates two copies of the input signal.
i. The first output is given to one LMX2594, which outputs two RF clocks. These two RF clocks are given to first and second ADC as sampling clocks.
ii. Similarly, the second output is given to second LMX2594 to generate two RF clocks. These RF clocks are given to third and fourth ADC as sampling clocks.
b. The second copy is given to LMK04828. It generates the SYSREF signals for 4 ADCs, SYSREF for FPGA, MGT clocks for JESD data transmission and also generates SYNC and SYSREFREQ for LMX ICs.
2. The SYNC signal generated by LMK04828 is buffered through LMK00304 to generate two copies of SYNC signal for the two LMX2594 ICs used for ADC sample clock generation.
3. Similarly, the SYSREFREQ generated by LMK04828 is buffered through LMK00304 to generate two copies and given to the two LMX2594 ICs as SYSREFREQ input.
Hi Pratiksha,
I believe we provided a clocking scheme based on your requirements already.
What has changed?
Regards,
Rob
Hi Pratiksha,
Pratiksha Halijwale1 said:LMK04832 supports maximum upto 7 SYSREF outputs
Unlike the LMK04828, every output on the LMK04832 can be routed as a SYSREF output, so actually the LMK04832 supports 14 differential SYSREF outputs.
Moreover, the LMK04832 allows 3.3V LVCMOS format on odd-numbered outputs and CLKout8/10, and permits dual single-ended signals of the same polarity out of the CLKout/CLKout* pins (datasheet Table 25 for a complete description). Even more, the LMK04832 allows individual SYSREF outputs to be glitchlessly masked during operation, so that only certain outputs are active at a time (datasheet Table 22 for a complete description)
By my count, you require 8 SYSREFs to the ADCs, 1 SYSREF to the FPGA, and 4 MGT_ADC clocks. This leaves one free LMK04832 output to handle the remaining SYNC/SYSREF_REQ operation to the two LMX2594. But you are not using the LMX2594 to generate SYSREF requests (diagram shows RFoutB going to an ADC), so actually you only need two LVCMOS SYNC signals. The remaining LMK04832 output can just be configured as two single-ended SYNC signals, and no DS90LV032A or any other buffer is required.
Depending on which LMK04832 CLKout you use for the LMX SYNC signals, the other output in that pair may also activate and produce a SYSREF output. For example, if you placed your FPGA SYSREF on CLKout2 and your LMX SYNC signals on CLKout3, even if you masked the other SYSREF outputs, attempting to produce a SYNC signal from CLKout3 would also elicit a pulse from CLKout2. As long as your FPGA or ADC SYSREF input can be temporarily disabled or ignored while the LMX2594 SYNC is taking place, there should be no issues grouping them together. Afterward, you can set INPIN_IGNORE in the LMX2594 to ignore noise on the SYNC pin and power down the output format buffer for the SYNC signals, to avoid accidentally SYNCing the LMX2594 clocks while issuing SYSREF pulses.
Regards,
