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ADS8685: How do I retry to get conversion result from ADS8685?

Takuya
Prodigy 50 points

Part Number: ADS8685

Three ADS8685-s connect to FPGA(MAX10) with daisy-chain.
The FPGA communicates with the converters by SPI(not multi-SPI). The FPGA is SPI master.

ADS8585 has parity check, so I think that FPGA can find a error on transmission by using parity error.
If an error get occurred, I will retry to get the same conversion result.

Question 1: Can ADS8685 output the same result? (Can it retry?)
Question 2: How FPGA get the same result? I want to know the sequences to get the result.


According to the datasheet(ads8685.pdf, revC) p39 Figure 73, this converter outputs once conversion result when FPGA sends more than 32 SCLKs.

  • 0
    TI__Mastermind 49515 points

    Hi Takuya,

    The output data is still there and not changed without any new CONVST/CS signal, however I do not think you get the same data again. A data transfer begins at the falling edge of the CONVST/CS signal and the host controller pulls CONVST/CS low to initiate a data transfer, the ADC takes control of the data bus and the contents of output data word are loaded into the output shift register, the MSB of the output shift register data is shifted out on the SDO pin on the launch edge of the SCLK.

    When you find an error on the data transmission in the frame F, the data have been shifted out to the SDO within the first 16 SCLKs. If more SCLKs >32 are received, the data on the SDO will be 0. Hence, you can not get the data again in the same frame.

    If you want to pull CONVST/CS back to high then to low to initiate a new data transfer in the frame F+1, the conversion data will be updated because a new data conversion has been initiated on the rising edge of the CONVST/CS signal.

    Thanks&regards,

    Dale

  • 0 in reply to Dale Li
    Prodigy 50 points

    Hi Dale,

    Thank you for replying.
    Do you mean that this converter don't send the same conversion result?

    (I'm not good at English, so please let me confirm that.)

    Best regards.

    Takuya

  • 0 in reply to Takuya
    TI__Mastermind 49515 points

    Hi Takuya,

     A data transfer begins at the falling edge of the CONVST/CS signal which is initiated by your host controller, the ADC loads the conversion data into the output shift register also the SDO line at the falling edge of SCLK for SPI-00 mode, thus there is no any problem for the ADC to send the conversion data. The problem is, when you pull the CONVST/CS signal back to high (rising edge) then pull it to low (falling edge) for reading the conversion data, the previous conversion data you are trying to read 2nd time has been updated because the same CONVST/CS pin is a dual functionality pin, the rising edge of the  CONVST/CS signal has triggered a new data conversion.

    I hope this helps you understand.

    Thanks&regards,

    Dale

  • 0 in reply to Dale Li
    Prodigy 50 points

    Hi Dale,

    I understood.

    Summary:
    - The data will be output 0 if more than 32 SCLKs in the frame F. Therefore I cannot get the same result in the same frame.
    - With a new CONVST/CS signal, the ADC outputs is updated in the frame F+1.

    Thank you very much for your helps. I'm sorry to bother you.

    Regards.