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ADS7853: ADS7853 CFR readback with 32 spi clk cycles

Part Number: ADS7853

Hi,

as mentioned in the datasheet of ADS7853 figure 90., to read back the configuration register (CFR) you have to use 48 SPI clocks. As it is easier for our system to integrate we would just want to use 32 SPI clock sequences, but still use the CFR readback feature to confirm the ADC is working as intended.

So we just tried to read back the CFR with 32 SPI clocks and it works fine. Can you confirm that this is intended and not going to be changed/bugfixed in future revisions ? Cause that would be really bad if we would rely on a feature thats not officially supported and changed afterwards.


Thanks for your answer.

Greetings,

Steve 

  • Hello,

    This is not an intended use of the device. The device configuration is likely why the customer is seeing the information they need, but that may change and could be losing out on information. 

    The device will not be going through any changes, thus this is not something to be concerned about. 

    Regards

    Cynthia

  • Hello Cynthia ,

    thank you for your answer. I dont exactly know how to interprete your second sentence ("...but that may change and could be losing out on information"). What do you exactly mean by that or can you give an example ?  

    Our application is simple. We configure the ADC at the power up of our system and beside the normal ADC conversions we want to check periodically that the configuration remains the same on runtime.

  • Let me explain further

    The read back requires 48 SCLK, when using only 32 SCLK, that means that the last 16 bits of read back data is not being looked at. This information is being lost. 

    If the information in the last 16 bits is not important to the customer and they feel comfortable with that loss of information.

    Regards

    Cynthia

  • Ok, now i got it :). Thank you for your explanation.