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ADS8166: SPI timing

Gregory Duperon
Expert 6030 points
Part Number: ADS8166

I have a customer planning to run the device at 3.3V.

What is the value of td_CKDO for 2.35 <= DVDD <= 5.5V for a 70MHz clock frequency?

  • 0
    TI__Mastermind 36150 points

    Hi Gregory,

    I will need to follow-up with the design team to see if we can provide a specific number.  However, for 2.35 <= DVDD <= 5.5V, the device will support a 70MHz SCLK frequency, which requires td_CKDO to be less than 1/70M, or <14.2nS.  

    The ADS8166 operates in early data launch mode, which means that it launches data on the same clock edge as the host captures.  This allows td_CKDO to be longer than 1/2 of the SCLK period and still meet timing requirements.

    I will respond back within 1 business day with an update.

    Thanks!

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    TI__Mastermind 36150 points

    Hi Gregory,

    We are researching the data to see if we can find any additional information.

    I will provide another update by Tuesday of next week.

    Thanks,
    Keith

  • 0 in reply to Keith Nicholas
    TI__Mastermind 36150 points

    Hi Gregory,

    We have not found any additional data.  At this point, I am going to close out this thread, but feel free to make another post if there are additional questions.

    Regards,
    Keith