ADC08D1020: Interleaving ADC1 & ADC2 channel with Extended mode

Hi Nicolas,

I will need to address this with design and confirm.

I will get back to you.

Regards,

Rob

Hi Nicolas,

I apologize, I am still waiting to hear back from design for a confirmation on this.

It is not clear to me either on the EVM setup or datasheet if the two ADC channels are separate controls for offset and timing adjust in DES mode.

Regards,

Rob

Bonjour,

Are the test you did with the EVM in DES mode? According to what follows, we are unable to have two independent offset and gain control in DES mode!

Here are the two files containing the resulting of a 2D sweep of the offset and fullscale on input I.
Values for offset and fullscale of channel Q are left to zero.
One file is with the ADC configured using DES, the second without.
The value I and value Q in the files are the average of 60'000 ADC output samples (30'000 each).
The inputs of the ADC are connected to a constant voltage.

We can see that in Non-DES mode (on the left), the ADC I has its output value changing according to the offset and fullscale values written to the channel I registers, whereas the output value of ADC Q does not change, according to the constant offset and fullscale values written to channel Q registers.

On the other hand, in DES mode (on the right), the output of both ADC I and ADC Q are changing according to offset and fullscale values written to the channel I register of the ADC, even if the values written to offset and fullscale registers of channel Q are kept constant to zero.

Non-DES registers
0x00007fff Calibration Register
0x0000b1ff Configuration Register
0x0000007f Channel I Offset
0x0000807f Channel I Full Scale
0x0000007f Channel Q Offset
0x0000807f Channel Q Full Scale
0x000003ff Extended Configuration
0x0000007f Phase Coarse Adjust
0x000000ff Phase Fine Adjust

DES registers
0x00007fff Calibration Register
0x0000b1ff Configuration Register
0x0000007f Channel I Offset
0x0000807f Channel I Full Scale
0x0000007f Channel Q Offset
0x0000807f Channel Q Full Scale
0x000023ff Extended Configuration
0x0000007f Phase Coarse Adjust
0x000000ff Phase Fine Adjust

(In bold, the registers that are changing their value during the 2D sweep.)

#offsetI scaleI offsetQ scaleQ valueI valueQ
-256 -256 0 0 60.1753 52.2227
-256 -192 0 0 56.7137 52.2009
-256 -128 0 0 53.4288 52.1593
-256 -64 0 0 50.8673 52.1906
-256 0 0 0 48.3136 52.2219
-256 64 0 0 46.0896 52.2333
-256 128 0 0 44.1483 52.2559
-256 192 0 0 42.2558 52.2766
-256 255 0 0 40.6251 52.2243
-192 -256 0 0 64.7182 52.2841
-192 -192 0 0 61.0056 52.1914
-192 -128 0 0 57.6027 52.2507
-192 -64 0 0 54.6645 52.1887
-192 0 0 0 51.9897 52.198
-192 64 0 0 49.7289 52.1943
-192 128 0 0 47.6025 52.2282
-192 192 0 0 45.611 52.2294
-192 255 0 0 43.8263 52.2231
-128 -256 0 0 69.6481 52.2754
-128 -192 0 0 65.3619 52.254
-128 -128 0 0 61.8981 52.1919
-128 -64 0 0 58.8508 52.2462
-128 0 0 0 55.9963 52.2093
-128 64 0 0 53.3394 52.1554
-128 128 0 0 51.0952 52.1896
-128 192 0 0 48.9731 52.2554
-128 255 0 0 46.9874 52.2368
-64 -256 0 0 74.4625 52.2347
-64 -192 0 0 70.0358 52.2281
-64 -128 0 0 66.186 52.1996
-64 -64 0 0 62.8471 52.2539
-64 0 0 0 59.9475 52.2335
-64 64 0 0 57.147 52.2279
-64 128 0 0 54.7931 52.2163
-64 192 0 0 52.3996 52.2485
-64 255 0 0 50.231 52.2499
0 -256 0 0 79.5498 52.2234
0 -192 0 0 74.9646 52.2522
0 -128 0 0 70.8841 52.2993
0 -64 0 0 67.1832 52.2165
0 0 0 0 64.0409 52.2237
0 64 0 0 61.0975 52.1999
0 128 0 0 58.6097 52.2188
0 192 0 0 56.0439 52.2124
0 255 0 0 53.9484 52.257
64 -256 0 0 84.9453 52.2539
64 -192 0 0 79.8911 52.2341
64 -128 0 0 75.648 52.2486
64 -64 0 0 71.9778 52.1838
64 0 0 0 68.3577 52.1606
64 64 0 0 65.1673 52.1494
64 128 0 0 62.4925 52.1853
64 192 0 0 60.0001 52.1445
64 255 0 0 57.5487 52.1627
128 -256 0 0 89.8604 52.1912
128 -192 0 0 84.4989 52.2437
128 -128 0 0 79.9471 52.1503
128 -64 0 0 76.0572 52.1381
128 0 0 0 72.4136 52.155
128 64 0 0 69.0421 52.2498
128 128 0 0 66.0285 52.1876
128 192 0 0 63.2109 52.2341
128 255 0 0 60.9649 52.1719
192 -256 0 0 94.7238 52.2174
192 -192 0 0 89.061 52.2465
192 -128 0 0 84.1816 52.2292
192 -64 0 0 80.0194 52.2271
192 0 0 0 76.2021 52.2365
192 64 0 0 72.9107 52.2327
192 128 0 0 69.7313 52.2355
192 192 0 0 66.7512 52.3088
192 255 0 0 64.0166 52.2415
255 -256 0 0 99.4453 52.2592
255 -192 0 0 93.3654 52.2243
255 -128 0 0 88.2947 52.1916
255 -64 0 0 83.863 52.1288
255 0 0 0 79.8154 52.1723
255 64 0 0 76.3003 52.2033
255 128 0 0 73.1414 52.2331
255 192 0 0 70.0218 52.2079
255 255 0 0 67.1331 52.2236

#offsetI scaleI offsetQ scaleQ valueI valueQ
-256 -256 0 0 60.8623 60.4085
-256 -192 0 0 57.3164 56.865
-256 -128 0 0 54.0411 53.8062
-256 -64 0 0 51.197 50.9504
-256 0 0 0 48.8786 48.5853
-256 64 0 0 46.7538 46.2164
-256 128 0 0 44.7249 44.2211
-256 192 0 0 42.804 42.2975
-256 255 0 0 41.0273 40.8548
-192 -256 0 0 65.3236 64.9109
-192 -192 0 0 61.6257 61.0949
-192 -128 0 0 58.1995 57.821
-192 -64 0 0 55.1628 54.9445
-192 0 0 0 52.4917 52.2099
-192 64 0 0 50.1067 49.9385
-192 128 0 0 48.0061 47.7136
-192 192 0 0 45.936 45.7335
-192 255 0 0 44.0402 43.9262
-128 -256 0 0 70.0655 69.6798
-128 -192 0 0 65.8753 65.5499
-128 -128 0 0 62.1868 62.0502
-128 -64 0 0 59.1908 58.9122
-128 0 0 0 56.1971 56.1086
-128 64 0 0 53.7187 53.6124
-128 128 0 0 51.3608 51.2084
-128 192 0 0 49.1233 49.0342
-128 255 0 0 47.2759 47.0634
-64 -256 0 0 74.9549 74.8416
-64 -192 0 0 70.4489 70.2835
-64 -128 0 0 66.6517 66.3614
-64 -64 0 0 63.1941 63.0798
-64 0 0 0 60.1894 60.0729
-64 64 0 0 57.5766 57.2361
-64 128 0 0 55.0087 54.9403
-64 192 0 0 52.7142 52.7327
-64 255 0 0 50.5604 50.4909
0 -256 0 0 79.9474 79.7529
0 -192 0 0 75.251 75.226
0 -128 0 0 71.2036 71.1402
0 -64 0 0 67.4724 67.5347
0 0 0 0 64.2538 64.2479
0 64 0 0 61.4371 61.2903
0 128 0 0 58.9809 58.8783
0 192 0 0 56.2844 56.3002
0 255 0 0 54.0146 54.0085
64 -256 0 0 85.2692 85.095
64 -192 0 0 80.1408 80.019
64 -128 0 0 75.8836 75.9488
64 -64 0 0 72.0206 72.0464
64 0 0 0 68.5729 68.4953
64 64 0 0 65.2598 65.3122
64 128 0 0 62.6312 62.7725
64 192 0 0 60.0372 60.1152
64 255 0 0 57.7762 57.6001
128 -256 0 0 90.0922 89.9988
128 -192 0 0 84.7304 84.7611
128 -128 0 0 80.0778 80.1277
128 -64 0 0 76.0513 76.269
128 0 0 0 72.5767 72.736
128 64 0 0 69.1488 69.1413
128 128 0 0 66.1259 66.1699
128 192 0 0 63.3066 63.456
128 255 0 0 60.9674 61.0076
192 -256 0 0 94.6902 94.7692
192 -192 0 0 89.1534 89.0989
192 -128 0 0 84.2579 84.2707
192 -64 0 0 80.0439 80.1023
192 0 0 0 76.1045 76.4851
192 64 0 0 72.9507 73.0673
192 128 0 0 69.863 69.9071
192 192 0 0 66.8887 66.9564
192 255 0 0 64.0747 64.1823
255 -256 0 0 99.2397 99.7632
255 -192 0 0 93.428 93.6723
255 -128 0 0 88.3245 88.3098
255 -64 0 0 83.8815 84.0462
255 0 0 0 79.9066 80.0474
255 64 0 0 76.1981 76.6177
255 128 0 0 73.0705 73.3188
255 192 0 0 70.0061 70.096
255 255 0 0 67.0564 67.2165

Bonjour,

I tried the following sequence between each step of the sweep, and the result is still the same. Both output values of ADC I and ADC Q follow the output and fullscale values of channel I registers.

DES registers
0x000003ff Extended Configuration -> Reset DES mode bit
0x0000007f Channel I Offset
0x0000807f Channel I Full Scale
0x0000007f Channel Q Offset
0x0000807f Channel Q Full Scale
0x000023ff Extended Configuration -> Set DES mode bit
0x0000007f Phase Coarse Adjust
0x000000ff Phase Fine Adjust

So, no. It does not solve the issue.

Best regard
Didier

Hi Didier,

Here is what I am suggesting....

Non-DES registers
0x00007fff Calibration Register
0x0000b1ff Configuration Register
0x0000007f Channel I Offset
0x0000807f Channel I Full Scale
0x0000007f Channel Q Offset
0x0000807f Channel Q Full Scale
0x000003ff Extended Configuration
0x0000007f Phase Coarse Adjust
0x000000ff Phase Fine Adjust

Then, put into DES mode.

Then, acquire the analog signal.

Regards,

Rob

Bonjour Rob,

Here's what I tried in my 2D sweep loop.
Note that I had to add the Resistor Trim Disable bit so that the DCLK do not stop when writing the configuration register.

0x00007fff; Set Calibration
0x000043ff; Set Extended Configuration -> Set the Resistor Trim Disable bit (DCLK must not stop)
0x0000b1ff; Set Configuration Register
0x0000c07f; Set Channel I Offset
0x0000407f; Set Channel I Full Scale
0x0000007f; Set Channel Q Offset
0x0000807f; Set Channel Q Full Scale
0x000043ff; Set Extended Configuration -> Non-DES mode
0x0000007f; Set Phase Coarse Adjust
0x000000ff; Set Phase Fine Adjust
0x000063ff; Set Extended Configuration -> DES mode

Result still the same.

Could it really help to write first the offset and fullscale registers to the default value, and then to the value I want?

Best regards
DIdier

Hi Didier,

Please try this sequence.....and let me know if you see any changes in DES mode.

this is what I do on the WaveVision5 Software and I can see changes to both I and Q channels, then I put it in DES mode.

0x00007fff; Set Calibration
0x000003ff; Set Extended Configuration
0x0000c07f; Set Channel I Offset
0x0000407f; Set Channel I Full Scale
0x000023ff; Set Extended Configuration -> DES mode

Thanks,

Rob

Bonjour Rob,

I'm sorry but I guess I have not explained clearly my issue.

Indeed, you wrote: "I can see changes to both I and Q channels". That's my problem! When I write to the channel I register, I would like to see the changes applied only to the samples coming out of the ADC I. Even in DES mode. And it's not what I'm experiencing.

Trying to get a better mutual understanding, we prepared two diagrams describing the internal layout of the ADC08D1020. In each of them, there are:

• two inputs, I and Q,
• two ADC, I and Q,
• a Crosspoint Switch (CPS), routing the inputs to the ADC depending on DES mode and I/Q selection*, and
• the I and Q adjustable gain/offset controls.

They differ in the position of the I and Q adjustable gain/offset controls: they can be placed before the CPS, or after the CPS.

Gain/Offset Controls BEFORE the CPS.

Gain/Offset Controls AFTER the CPS.

Could you tell us which of these two layouts best describes the internals of the ADC08D1020?

Best regards
Didier

*: CPS logic depends Extended Configuration register bits 12 (Input Selector I or Q) and 13 (DES Enable).

Hi Didier,

No problem. I apologize for the confusion. 

The second diagram is correct, where the CPS is first/before the gain/offset and ADCs.

You should be able to change the gain & offset in either ADC (I or Q or both I&Q) first, but this must be done in nonDes mode.

Then once those changes are applied, change the device to Des Mode (input I or Q).

Those changes previously applied should hold in this new mode change.

Let me know if that helps. If not, we can take this offline and have a quick call to go over any remaining questions.

Regards,

Rob

Bonjour Rob,

Unfortunately, it does not help. Im still seeing both ADC I and ADC Q samples varying when changing only offset I.

Maybe could you help me.

Let's say my use case has two steps, Both steps wants 2GS/s in DES mode, without stopping the DCLK between the steps (constant signal on both inputs).
First step, I want to set channel I offset to +128 and channel Q offset to -128, and get samples.
Second step, I want to set channel I offset to -128 and channel Q offset to +128, and get samples.

After the first step, due to the difference in offsets, samples from ADC I should be higher than samples from ADC Q,
whereas after the second step, due to the reversed difference in offsets, samples from ADC I should be lower than samples from ADC I.

0x00007fff; Set Calibration
0x000003ff; Set Extended Configuration
0x0000407f; Set Channel I Offset +128
0x000040ff; Set Channel Q Offset -128
0x000023ff; Set Extended Configuration -> DES mode
-> Here I am getting samples for Step One
-> For Example (I then Q): 72 60 72 60 72 …
0x000003ff; Set Extended Configuration -> Non-DES mode
0x000040ff; Set Channel I Offset -128
0x0000407f; Set Channel Q Offset +128
0x000023ff; Set Extended Configuration -> DES mode
-> Here I am getting samples for Step Two
-> For Example (I then Q): 60 72 60 72 60 …

I want that samples from Step One show ADC I values higher than ADC Q values.
I want that samples from Step Two show ADC I values lower than ADC Q values.

All I have tried until now fails to show this expected result.

If you could provide me with the register writes I am missing to acheive my goal of these two successive steps, it would be a great help.

Thanks in advance
Didier

Hi Didier,

I will run this scenario you described above on the EVM tomorrow and capture the waveforms and let you know what I find.

Regards,

Rob

Hi Didier,

See the two attached files. 
I configured the part only with no changes to either I or Q channels.

Then I changed just the I channel to an offset of 48. This was the only change applied.

Both outputs are the device configured for DESI.

If you send me all the registers with the writes you have shown above, I can plug this in manually in the WaveVision GUI to see if I can find an error.

Unfortunately, this GUI is very old, and I cannot create a log file on the reg writes I put in and some buttons are tied to reg writes that as well and are not marked appropriately, so I think there is a missing step in the process that I cannot see.

Help me work through this backwards and we will get you going!

Regards,

Rob

DESI_Unchanged.Time_Domain_Exported_DataDESI_Changed_CHI_Offset=48_Only.Time_Domain_Exported_Data

Bonjour Rob,

Here are two files. ADC08D1020-00.log contains all the writes to the registers of the ADC08D1020. They are mapped sequentially from address 0x4440. There are also other reads and writes to another register (at address 0x4400). This register controls some pins of the ADC, mainly to set power, start calibration, and poll for calibration complete.

There are two locations where the test pattern is enabled, then disabled. It is used to calibrate our receiver of the ADC samples.
I've also cleaned up the code to avoid writing to a register the same value it was already written. This would hopefully help us starting with a smaller list.

Second file contains the data read. Header line contains I offset, I fullscale, Q offset Q gain, odd samples average, even samples average, and the first eight samples. I reproduced it below.

#offsetI scaleI offsetQ scaleQ ch1 ch2
0 0 0 0 63.9067 64.0009 64 64 63 64 64 64 64 64
48 0 0 0 67.133 67.4074 67 68 67 67 67 67 67 67

From this point, I am waiting for your insight about what to change in my sequence of register writes to get the result I want, i.e. the second line of data showing alternating values 67 64 67 64 67 64 ...

Thanks for your help.
Didier

#offsetI scaleI offsetQ scaleQ ch1 ch2
0 0 0 0 63.9067 64.0009 64 64 63 64 64 64 64 64
48 0 0 0 67.133 67.4074 67 68 67 67 67 67 67 67

--> Initialize
0x00004400 <- 0x0000101e; Get initial value of ADC External Control
0x00004400 -> 0x0000101e; Initialize ADC External Control
0x00004400 -> 0x0000101f; Power up ADC
0x00004440 -> 0x00007fff
0x00004444 -> 0x0000b1ff; Set Configuration Register
0x00004448 -> 0x0000007f; Set Channel I Offset
0x0000444c -> 0x0000807f; Set Channel I Full Scale
0x00004468 -> 0x0000007f; Set Channel Q Offset
0x0000446c -> 0x0000807f; Set Channel Q Full Scale
0x0000447c -> 0x0000007f; Set Phase Coarse Adjust
0x00004478 -> 0x000000ff; Set Phase Fine Adjust
0x00004464 -> 0x000043ff; Set Extended Configuration
0x00004400 -> 0x0000001f; Clear Cal Run
0x00004400 <- 0x0000001f; Read to ensure PCIe flush
0x00004400 -> 0x0000101f; Set Cal Run
0x00004400 <- 0x0000301f; Read to ensure PCIe flush
0x00004400 <- 0x0000301f; Poll for ADC Cal done
0x00004400 <- 0x0000301f; Poll for ADC Cal done
0x00004400 <- 0x0000101f; Poll for ADC Cal done
0x00004464 -> 0x0000c3ff; Enable Test Pattern Output
0x00004464 -> 0x000043ff; Disable Test Pattern Output
--> Configure
0x00004464 -> 0x000063ff; Set Extended Configuration
0x00004464 -> 0x0000e3ff; Enable Test Pattern Output
0x00004464 -> 0x000063ff; Disable Test Pattern Output
--> Configure Offset 0 (do nothing)
0x00004464 -> 0x000063ff; Set Extended Configuration
0x00004464 -> 0x000063ff; Set Extended Configuration
============> Read Data
--> Configure Offset 48
0x00004464 -> 0x000043ff; Set Extended Configuration
0x00004448 -> 0x0000307f; Set Channel I Offset
0x00004464 -> 0x000063ff; Set Extended Configuration
============> Read Data
--> Back to normal
0x00004464 -> 0x000043ff; Set Extended Configuration
0x00004448 -> 0x0000007f; Set Channel I Offset
0x00004464 -> 0x000063ff; Set Extended Configuration

Thank you Didier,

Let me look into this and get back to you.

Regards,

Rob

Hi Didier,

We looked at the sequence and everything looks fine to us.

We have one question: Are you applying an analog input signal to both the I & Q Channels? It isn't clear to us.

When capturing the data with the test pattern enabled or with no input signal applied, you won't be able to see any offset, gain changes, etc.

Please confirm.

Thx,

Rob

Bonjour Rob,

We are applying a constant signal to both I  Q inputs.

The test pattern is not enabled when we are reading the samples we want, with the I and Q offsets changed.
(As you can see in our log, it is enabled twice during the Init & Config of our system to calibrate the samples receiver.)

The inputs I and Q are connected to a constant signal. Is it what you name "no input signal"?

Do I understand correctly that the offset applied to the I and Q channels cannot be seen unless there is a non-constant signal applied?

I'll be out-of-office with barely access to the Internet for one week.
I'm sorry I'm not sure I'll get in touch in touch in the coming days.

Best regards
Didier

Hi Didier,

No. The offset applied to the I and Q channels cannot be seen unless there is constant signal applied.

Please reach out when ready to resume testing.

Regards,

Rob

Bonjour Rob,

We are using two of your ADC: the ADC08D1020 and the ADC08D500.

I ran the same program on the ADC08D500. That was just to check the behavior of the software.

Respective to the small changes in register definitions, the program runs the same operations:
- constant voltage on inputs,
- set first offsets on input I (same on input Q),
- enable DES mode,
- get samples,
- disable DES mode,
- set second offset on input I (different from input Q),
- enable DES mode,
- get samples.

With the ADC08D500, different offsets on input I and input Q show one sample out of two changing according to the offset.
    #offsetI scaleI offsetQ scaleQ ch1 ch2
    0 0 0 0 45.0326 45.098 45 46 45 45 45 45 45 45
    48 0 0 0 45.115 48.9525 45 49 45 49 45 49 45 49

With the ADC08D1020, different offsets on input I and input Q show all the samples changing according to the offset.
    #offsetI scaleI offsetQ scaleQ ch1 ch2
    48 0 0 0 54.1932 54.1384 54 55 54 55 54 54 55 54
    0 0 0 0 51.0355 51.0061 51 51 51 51 51 51 51 51

Into another direction, I've tried to set the offset of input I from the start to 48 (keep offset Q to 0), and only in a second time change to to zero.
0x0000000000004400 <- 0x0000101e; Get initial value of ADC External Control
0x0000000000004400 -> 0x0000101e; Initialize ADC External Control
0x0000000000004400 -> 0x0000101f; Power up ADC
0x0000000000004440 -> 0x00007fff
0x0000000000004444 -> 0x0000b1ff; Set Configuration Register
0x0000000000004448 -> 0x0000307f; Set Channel I Offset
0x000000000000444c -> 0x0000807f; Set Channel I Full Scale
0x0000000000004468 -> 0x0000007f; Set Channel Q Offset
0x000000000000446c -> 0x0000807f; Set Channel Q Full Scale
0x000000000000447c -> 0x0000007f; Set Phase Coarse Adjust
0x0000000000004478 -> 0x000000ff; Set Phase Fine Adjust
0x0000000000004464 -> 0x000043ff; Set Extended Configuration
0x0000000000004400 -> 0x0000001f; Clear Cal Run
0x0000000000004400 <- 0x0000001f; Read to ensure PCIe flush
0x0000000000004400 -> 0x0000101f; Set Cal Run
0x0000000000004400 <- 0x0000301f; Read to ensure PCIe flush
0x0000000000004400 <- 0x0000301f; Poll for ADC Cal done
0x0000000000004400 <- 0x0000301f; Poll for ADC Cal done
0x0000000000004400 <- 0x0000101f; Poll for ADC Cal done
0x0000000000004464 -> 0x0000c3ff; Enable Test Pattern Output
0x0000000000004464 -> 0x000043ff; Disable Test Pattern Output
0x0000000000004464 -> 0x000063ff; Set Extended Configuration
0x0000000000004464 -> 0x000043ff; Set Extended Configuration
0x0000000000004448 -> 0x0000307f; Set Channel I Offset
0x0000000000004464 -> 0x000063ff; Set Extended Configuration
--> Get Samples
0x0000000000004464 -> 0x000043ff; Set Extended Configuration
0x0000000000004448 -> 0x0000007f; Set Channel I Offset
0x0000000000004464 -> 0x000063ff; Set Extended Configuration
--> GetSamples
0x0000000000004464 -> 0x000063ff; Set Extended Configuration

I expect only one sample out of two to change according to the offset. I keep get all samples changing.
    #offsetI scaleI offsetQ scaleQ ch1 ch2
    48 0 0 0 54.1932 54.1384 54 55 54 55 54 54 55 54
    0 0 0 0 51.0355 51.0061 51 51 51 51 51 51 51 51

I'd really need you provide me with a list of register writes from your WaveVision software.

Maybe another thing to check: Are there any variations into the ADC08D1020 chips?
Could there be any difference between the part I am exercising and the part you are exercising?
Is there a way to check that they are really the same, such as a version number, revision number, or…?

Thanks for your help.
Best regards
Didier

Hi Didier,

I forwarded an email to Nicolas Schlumpf. As he was the person that started this E2E question.

There is no way to download the register settings that are applied in Wavevision unfortunately. I looked into that.my guess is that there is something in the background that is being done, or something is not being applied correctly on your side.

Can you respond to the email I sent to Nick and we can take this offline to resolve.

Thanks,

Rob

Hi Rob,

Could You please answer Didier's questions;

Maybe another thing to check: Are there any variations into the ADC08D1020 chips?
Could there be any difference between the part I am exercising and the part you are exercising?
Is there a way to check that they are really the same, such as a version number, revision number, or…?

Regards,

N.

Hi Nicolas/Didier,

Nothing has changed with the part or product. There are not different variations within the product as well. That would allow or not allow certain features.

There are no differences between the part I am testing and the one you have.

I would like to take this offline and setup a conf call to discuss this. Can you please send me an email address to best contact you?

Regards,

Rob

Hi Rob,

The e-mail address of Didier is didier.trosset@acqiris.com and the one of me is nicolas.schlumpf@acqiris.com

Regards,

Nicolas