ADC clock and peripheral circuit design issues

Jenson

1.What is the relationship between ADC clock and sampling rate? Is the sampling rate correspondingly larger if the clock frequency is larger?

2.How to choose a suitable driver op amp for SAR ADC? What information should be paid attention to?

3.How to design the RC of SAR ADC? What factors are involved in the design of RC? Is there a detailed description document?

over 5 years ago

0 Collin Wells over 5 years ago

TI__Guru 64715 points

Hello,

All of these questions and more are answered in the TI Precision Labs ADCs video series:

https://training.ti.com/ti-precision-labs-adcs

The section on design SAR ADC Front-End Drive Circuitry will directly address the information you're looking for:

https://training.ti.com/ti-precision-labs-adcs-introduction-sar-adc-front-end-component-selection?context=1139747-1140267-1128375-1139106-1128643

0 Jenson over 5 years ago in reply to Collin Wells

TI__Intellectual 2475 points

Hi，

I have watched these videos, but the information is not detailed enough. For example, it did not explain the clock problem, nor did it explain how the RC design would be better. So I have a few more detailed questions, as shown below.

1.What is the relationship between ADC clock and sampling rate? Is the sampling rate correspondingly larger if the clock frequency is larger?

2.How to choose a suitable driver op amp for SAR ADC? What information should be paid attention to?

3.How to design the RC of SAR ADC? What factors are involved in the design of RC? Is there a detailed description document?

0 Collin Wells over 5 years ago in reply to Jenson

TI__Guru 64715 points

Hello,

This material is definitely covered in those videos. I can provide short answers but then will direct you back to the videos as I assure you it's covered in greater detail than we can provide in an E2E exchange.

1.) For a SAR ADC the timing between the digital action that begins the acquisition phase (CONVST or /CS) determines the sampling rate. This is shown in Slide 15 of 7.1 that shows how the sampling rates and acquisition times are calculated.

2.) A high level reason of the requirement is shown in video 7.1 in the first several slides. The design process is covered in great detail in the "Selecting and Verifying the Driver Amplifier" video:

https://training.ti.com/ti-precision-labs-adcs-selecting-and-verifying-driver-amplifier?context=1139747-1140267-1128375-1139106-1134078

3.) This is covered in great detail in the "Refine Rfilt and Cfilt Values" video:

https://training.ti.com/ti-precision-labs-adcs-refine-rfilt-and-cfilt-values?context=1139747-1140267-1128375-1139106-1134075

For some practical circuit design examples, please review the following circuit cookbook circuits. You'll notice they refer back to the same videos for the theory that explains the calculations.

https://www.ti.com/lit/an/sbaa256a/sbaa256a.pdf?ts=1602684851397

https://www.ti.com/lit/an/sbaa375/sbaa375.pdf?ts=1602684911109

https://www.ti.com/lit/an/sbaa371/sbaa371.pdf?ts=1602684916087

https://www.ti.com/lit/an/sbaa253a/sbaa253a.pdf?ts=1602684840372

0 Jenson over 5 years ago in reply to Collin Wells

TI__Intellectual 2475 points

Appreciate what you do! I may have missed some key information in the video，These are very helpful to me.

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ADC clock and peripheral circuit design issues