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DDC114: Sample C code to control the ADC

Jonathan Geronga
Expert 7930 points
Part Number: DDC114

Hi Team,

We have a customer that has some couple of inquiries with DDC114 that we hope you can help us out.

- The customer is planing on controlling DDC114 in fNIRS circuit with a Atmega644P and wanted to ask if this has any sample C code?
They don't know how to synchronize the DDC with the LED driver, so that they want to know which data point corresponds to which LED. Is the clock from the microcontroller clean enough?

- Is it possible to do the readout with the SPI interface of the microcontroller? I.e. connecting DCLK to SCK and DOUT to MISO.
- What type of anti-aliasing filter do you recommend for the input of the ADC?

Looking forward to your comments in the above inquiries.

Thanks,

Jonathan

  • 0
    TI__Genius 11550 points

    Hi Jonathan,

    We don't have any sample C code for MCU to control the DDC114. Our current EVM is using FPGA to generate all the required signals for the DDC114. The MCU clock may be good enough for the DDC but we have no experience in Atmega644P. For the best performance, it is recommended to generate both clock signals (CLK and CONV) from the same clock source. For synchronizing the LED driver, they will probably need to use the CONV signal and some circuitry to gate the LED.  

    The DDC114 doesn't have a standard SPI interface for retrieving the data. However, the device DVALID, DOUT, and the MCU SPI SCK can be used to provide the required signals to retrieve the data. The DDC114 data sample consists of 20-bit (FORMAT = 1) so a standard MCU SPI will need 10x SPI operation to read all the 4 channels data and requires post-processing to get correct data for each channel. When FORMAT is set to 0, the lower 4-bit of the data is truncated so only 16-bit of data is used. In this case, we will still require 8x SPI operation and post-processing of the data.

    The frequency response of the gated integrator is shown in the DS (Figure 7 on page 12). Basically, it is a low pass response with the first zero set at 1/Tint. Traditionally, the device is used with signals with way lower bandwidths than this, and any noise from the integrator itself is already taken into account internally in the DDC. But if the input signal or noise can extend beyond Nyquist it will fold back.

    We have never recommended an anti-aliasing filter at the input of the DDC as most of the design doesn't require one. However, if any was to be designed, one would have to make sure especially that no noise would be added by those elements. For instance, a resistor to ground at the input adds a current noise of sqrt(4kTR)/R from zero to Nyquist. Also, large capacitors to ground at the input create an increase in the noise gain of the amplifier (see typical noise graphs vs input capacitance plots of the DS - page 6).

    I hope this helps with the design of the DDC114 in their system.  

    Thanks.

    -TC