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ADS54J60EVM: ADS54J60EVM

Yuval Minster
Intellectual 800 points

Part Number: ADS54J60EVM

HI,

I looked at the schematic of the eval board and saw that there are 2 clocks from the ADC eval board connected to the FPGA: FPGA_JESD_CLK and CLK_LAO_0.

I understand that FPGA_JESD_CLK is the clock for the JESD interface.

I do not understand what is the CLK_LAO_0. What is it used for?

Yuval

  • 0
    TI__Guru* 91947 points

    Yuval,

    Early versions of the Xilinx JESD204B IP required both a core clock and a reference clock. CLK_LAO_0 was used to provide a core clock for this interface. This was not required with the Altera FPGA interface. Newer versions of the Xilinx JESD204B IP does not require this clock either.

    Regards,

    Jim