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ADS124S08 load cell questions: resolution and layout concerns

SIDDHARTH ROY
Intellectual 510 points
Other Parts Discussed in Thread: ADS1243, ADS124S08, ADS1018, ADS114S08

Hi Bryan,

Thanks for your valuable inputs.

For point #1: I understand where your are coming from but as I mentioned the max swing of my input signal is from +6.25mV to -6.25mV. Multiplying it to gain of 128x will yield +/-800mV. If I use the excitation voltage as the Vref which is 5V, then then I am only using ~1/6 part of the full scale. Hence My idea was to give a stable external Vref of 1.25V so that the range is better utilized.

For point #2: Ok. I will place it near the ADC chip. but as I mentioned the SCLK and DIN are coming from the MCU and if the intent is to reduce ringing, generally resistors are placed near the source of the signal. You can give a re-thought.

Thanks,

Siddharth

  • 0
    TI__Guru 52896 points

    Hi Siddharth,

    I split this thread since we started talking about a different ADC (ADS124S08 instead of ADS1243). You can reference the original thread here: https://e2e.ti.com/support/data-converters/f/73/t/946419

    For #1, you need to consider if using a non-ratiometric reference to get more dynamic range is more important than the benefits of using a ratiometric voltage. What is the load cell resolution you are targeting? I see you have a max output signal of 6.25mV, so it would help to know how finely you need to be able to resolve this max output. This will tell you what dynamic range you require, and if using a lower reference voltage will actually benefit you.

    Also keep in mind that reference noise scales with input signal, so the more of your full-scale range that you use, the more reference noise you let into your system.

    For #2, it is more about decreasing the rise/fall times of the edges than the ringing of the signal lines. The sharp rise and fall times internal to the device will potentially cause additional noise within the ADC (mostly from the SCLK).  There will be some ringing due to trace inductance / capacitance and there is bound to be some standing waves due to a mismatch in the driving source and the high impedance of the CMOS input.  You can try to remedy this by reducing the drive strength of the push-pull outputs from the micro. Many ARM devices have this capability, but not all micros. Another method is by adding some series resistance to limit current which changes the charge/discharge capability of the driving source and in the process slows the edges.

    Is your MCU very far away from your ADC? If not, resistor placement might not be an issue either way. Is there a digital isolator between the ADC and MCU? If so, the isolator acts as the driving source, so you would still want to place the resistors close to the ADC. This is precisely what is happening on the EVM, as the MCU is placed between a level translator and the ADC. In this case as we want to allow customers to evaluate with an external MCU of their choice, so the resistors are placed closer to the ADC.

    Hope this all makes sense. If you have additional questions that are unrelated to these topics, please start a new thread and we will support you there.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Intellectual 510 points

    Hi Bryan,

    Thanks for all the inputs. Most of my queries are clear now.

    #1: For the resolution of the ADC, my requirement is to measure  2mBar pressure which corresponds ~0.29mV . So 1.25V should be optimum to go ahead as the external Vref.

    Thanks,

    Siddharth

  • 0 in reply to SIDDHARTH ROY
    TI__Guru 52896 points

    Hi Siddharth,

    Just to confirm, the output of your bridge is 6.25mV, and you only need to measure with a resolution of 0.29mV? So if the step size of 2mBar = 0.29mV, then the full-scale output is only ~43mBar? Maybe I misunderstood something here, but if this is the case then you very likely do not need a 24-bit ADC for this application. Even a 12-bit ADC like the ADS1018 has an input range setting of of +/-256mV with an LSB size of 0.125mV, far below your signal requirements.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Intellectual 510 points

    Hi Brian,

    Sorry, I missed to tell you that the o.29mV is after applying gain of 128x. So we want to capture a minimum signal of 0.29mV/128.

    Hope this clear your doubt.

    Thanks,

    Siddharth

  • 0 in reply to SIDDHARTH ROY
    TI__Guru 52896 points

    Thanks for clearing that up, Siddharth. Indeed that makes a difference.

    However, even then you are looking at 0.29mV / 128 = 2.3uV of resolution. If you look at the noise tables on pg. 22 in the ADS114S08 datasheet (16-bit version of the ADS124S08), you can see that at the lower data rates (<100SPS) and higher gains (>32) you are still getting a noise level of <2.3uV (RMS or PP).

    So, given your specifications, you will be able to resolve both the minimum (2.3uV) and maximum (6.25mV) signals that you need to measure. This means a 16-bit ADC would be sufficient for your application, even using a 5V reference voltage.

    It is up to you whether you choose the discrete 1.25V reference of the ratiometric 5V reference, but I wanted to make sure you had as much information as possible to make the most informed decision.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Intellectual 510 points

    Hi Bryan,

    Thanks for your valued information. At the moment I will go ahead with  1.25V Vref with 24 bit ADC. My data rate requirement is 200SPS. Because I need to sample 3 load cells with a data rate of atleast 60Hz each. 

    Thanks,

    Siddharth

  • 0 in reply to SIDDHARTH ROY
    TI__Guru 52896 points

    Hi Siddharth,

    Sounds good!

    If you have additional questions that are unrelated to this topic, please start a new thread and we will support you there.

    For now I will consider this topic resolved.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Intellectual 510 points

    Hi Bryan,

    One last question, if I am using external reference of 1.25V, I can use AVDD as 3.3V instead of 5V? I mean since my input swing is small, AVDD as 3.3V is optimum.

    Do you foresee any issues with this?

    Thanks,

    Siddharth

  • 0 in reply to SIDDHARTH ROY
    TI__Guru 52896 points

    Hi Siddharth,

    Yes you can use VREF = 1.25V with AVDD = 3.3V. Just make sure the differential and absolute reference voltage inputs adhere to the datasheet recommendations, highlighted in Table 7.3 below.

    Also keep in mind that if REFN is tied to ground (AVSS), you should disable the negative reference buffer.

    -Bryan