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ADS8698: Output Setup Time

Jordan Dahl
Prodigy 70 points
Part Number: ADS8698


The ADS869x datasheet specifies 25 ns minimum for "Setup time: SDO data valid to SCLK falling." It would be better for TI to spec an output pin with max propagation delay (clock edge to data valid). Is 25 ns specified assuming it is running at fmax (18 MHz)? The conversion to prop delay is simply clock period minus setup time, but I don't know what clock period to use. If 18 MHz, prop delay max is 55.5-25 = 30.5 ns. My actual frequency is 12.5 MHz, which gives 80-25 = 55 ns. Prop delay max should not actually vary with the clock frequency, so I would guess the correct value is 30.5? That would mean my actual setup time minimum is 80-30.5= 49.5 ns.

The SPI bus is routed through an isolation chip with significant delays. If I can't get more than 25 ns setup time (by slowing the clock) it is nearly impossible to meet timing.

  • 0
    TI__Mastermind 46055 points

    Hi Jordan,

    Regarding the delay time on the ADC, the tHT_CKDO should be considered because 

    • The output data is clocked out on SDO at the falling edge of SCLK.
    • The tHT_CKDO is the time of the SCLK falling to previous data valid on the SDO. Also, it's the delay time from the launch edge(falling edge) to the NEXT data valid on the SDO.

    Below is the block diagram for a typical time delay of data transfer between a controller and the ADC including a digital isolator,  the td_ckdo is the clock-to-data delay of the ADC device. Note that:

    • Your controller should be able to capture the data during tHT_CKDO of ADS8698 after the falling edge of SCLK (tHT_CKDO is td_ckdo in the picture)
    • The propagation delay of the digital isolator has a significant impact to the data capture, the total delay on the digital isolator is 2 x propagation delay of digital isolator.

    Hence, a digital isolator with a smaller propagation delay is needed. Otherwise, you may have to consider to capture the data on the controller by using a returned SCLK.

    The first page of the TechNotes can help you understand well:  Optimizing Data Transfer on High-Resolution, High-Throughput Data Converters

    For the timing parameter tsu_dock, it's characterized at the highest SCLK clock(18MHz).

    Best regards,

    Dale

  • 0 in reply to Dale Li
    Prodigy 70 points

    Hi Dale,

    Thanks for your response. You are right that the TechNote and the image are applicable here.

    The datasheet says at very minimum there is a 35 ns window when SDO is valid (25 setup plus 10 hold). I was hoping this window is actually larger for SCLK less than the maximum. Your suggestion to measure from the SCLK falling edge exacerbates the problem; that reduces the valid window to only 10 ns. Surely I have at least 35 ns to work with. I'd rather not change the schematic or components only because the ADC datasheet isn't clear.

    My basic question is trying to determine td_ckd maximum. I'm not sure it is right to say that tHT_CKDO from the datasheet is td_ckd. A prop delay value always has both a minimum (at the fastest PVT point) and a maximum (at the slowest PVT point). tHT_CKDO is equal to td_ckd minimum. I can only infer the maximum if I assume that tSU_DOCK is specified at the highest SCLK (18 MHz = 55.5 ns). Since you said that is true, then the max td_ckd is 55.5 ns - 25 ns = 30.5 ns. That should mean at 80 ns clock period there is 80 - 30.5 = 49.5 ns of setup time. If this is true, then it will work with my isolator delays. Does that seem like a valid conclusion?

  • 0 in reply to Jordan Dahl
    TI__Mastermind 46055 points

    Hi Jordan,

    Your understanding is correct. Actually, the lower SCLK(12.5Mhz<18MHz) definitely works for this ADC and no any issue to setup the signal. However, I do not know the propagation delay of your digital isolator. When the ADC receives the SCLK signal, it already has one propagation delay of digital isolator between the original SCLK signal from the controller and the output data from the ADC, it will have one more propagation delay of your digital isolator after the data goes through the digital isolator when the controller captures the data on the SDO. This is the key concern we usually have to consider when designing a data acquisition system with a digital isolator. We are thinking in different way, you consider if the ADC's timing parameters work with your digital isolator, actually we consider if the propagation delay of digital isolator has a significant impact to the timing of ADC for the controller.

    Regards,

    Dale