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ADS1278: Clock for sample rate of 144531 Samples/s

Marcus Bussek1
Prodigy 30 points
Part Number: ADS1278

Hi, I asked the support team but they could not help me.

We use the ADS1278 for a logging application. We have a sample rate of 144531 SA/s. At the moment the ADC clock is set to 37MHz.

Is that ok or is there a risk of some issues (esp. regadring the SNR), cause we need a clock of 144531 SA/s * 32bit *8 = 36.999.936Hz

You can find my support case here:

BR

Marcus

  • 0
    TI__Mastermind 46380 points

    Hello Marcus,

    Welcome to the TI E2E community.  Yes, you can operate at fclk=fsclk=36.999.936Hz and maintain full device performance.

    I am not able to see the details of your support case.  However, you can operate the ADS1278 at 37MHz (or any frequency less than this value down to 100kHz) and maintain full datasheet performance as long as the following requirements are met.

    1.  Must operate in Frame-Sync mode; SPI is only supported for clock rates up to 27MHz.

    2.  Since you are operating in TDM mode (all data shifted on DOUT1), SCLK and CLK should be continuous and set to the same frequency of 37MHz.

    3.  Vref must be in the range of 0.5V to 2.1V (fclk>32.768MHz).

    4.  DVDD must be in the range of 2V to 2.2V (fclk>32.768MHz).

    Regards,

    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 30 points

    Hi Keith

    thanks for your answer so far. My question is,

    is it ok to set the clock of the adc to 37MHz and use a sample-rate in the CPU of 144531 Samples / second?

    Our customer has doubts that the ADC clock does not match to the sample-frequency. I understand his point - now we need the information from your side if there could be any issues if we use a totally differenz ADC clock than the Sample-Rate .... e.g. ADC Cock 37MHz and a sample-Rate of 100 kSA/s.

    Is that also finde for the ADC and we get valid data? Or is there a requirement the the quotient of Sample-Rate and ADC-Clock has to meet?

    Regards Marcus

  • 0 in reply to Marcus Bussek1
    TI__Mastermind 46380 points

    Hello Marcus,

    The sample rate is set by the main clock, which in this case is 37MHz.  The actual output data rate will be 37M/256=144531.25sps.  The Frame Sync clock (Fsync) must be synchronized to the main CLK, and also be an exact integer number of CLK cycles.  SCLK must also be an exact integer number of CLK periods, and is typically set equal to CLK for maximum data rate.

    If I understand the question, the answer is NO.  The CPU generating SCLK and FSYNC must be synchronized to the main CLK, so that SCLK and FSYNC are integer multiple CLK cycles.  This requirement can be found in the Frame-Sync Format Timing Specification table.

    If you want to run at different data rates, you can change the filter settings, or the frequency of CLK, but in all cases, FSYNC period is determined by the CLK period and the filter settings.

    Regards,
    Keith

  • 0 in reply to Keith Nicholas
    Prodigy 30 points

    Hi Keith,

    thanks for your answer. So we know that we have to find solution. Perhaps the SW guys took that into account, but they have to double-check this.

    Thanks for your great support!

    BR

    Marcus