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ADS6245: channels alignment

Alon Cohen1
Prodigy 10 points

Part Number: ADS6245

Hi, 

Two questions about test patterns:

  1. I'm trying to align all four lvds data channels using two test patterns (all zeros, then all ones), hoping that the change will occur at the same sample (and create a delay in the design if not). The problem is that sometime the change is not "smooth" - an unexpected value is sampled for one (parallel) clock cycle between to two patterns, ruining the whole alignment concept described. Is that a known behaviour?
  2. Considering alternatives - I'm not sure how to use the toggle pattern. Toggling between 0101... to 1010... every clock can only determine the existence (or absence) of a delay between channels, but not which one is late. is that correct?

Thank you.

  • 0
    TI__Genius 12780 points

    Hi Alon,

    1. Are you using the SYNC pattern for this testing? I am not aware of this being an issue. Are you able to share what the data looks like across all 4 channels when running the test pattern?

    2. If you can trigger a capture in you FPGA (ILA) when you start the test pattern (like when the MSB changes to '1'), you could determine which channel arrived first. Have you been able to verify that a test pattern is working as expected, not just channel alignment?

    Best,

    Dan