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ADC3444: ADC input "kickback noise"

Ben van den Bergh
Intellectual 435 points
Part Number: ADC3444

Dear Forum members.

We are having some trouble with unwanted noise on the input of the ADC.

With absolutely no input signal connected to the input of the ADC only the passive input filter.

we are measuring noise with the oscilloscope (single ended) on Pin30 (INCM)

Please ask if you need further  information regarding the implementation or setup used.

Measurements made using small "spring" probe adapter to keep the GND return path as short as possible.

Scope set to 500MHz bandwidth.

Blue trace (CH 3) 30MHz clock input from (Y2) measured on the right hand side of R197. (Scope = DC coupled 1V/Div and +1V offset)

Yellow trace (CH 1) Pin 30 (INCM) measured on TP115. (Scope AC 50mV/Div coupled)

With CH 3 of the ADC switched off via a SPI command the noise reduces considerably.

Could this be a form of ADC "Kick back"

Please see below a screenshot of the input filter arrangement.

Thank you

Regards

  • 0
    TI__Mastermind 24940 points

    Hello Ben,

    The image of the input filter did not get uploaded correctly, would you please reupload it, using the "insert/edit media"

    From what I am gathering without looking at the schematic is there might be some crosstalk between the channels. The noise is present when other input sources are present, but the noise goes away when CH3 input source is removed, this leads me to believe that is the source of the issue

    Regards

    Cynthia

  • 0 in reply to Cynthia
    Intellectual 435 points

    Hi Cynthia,

    Please see above for detail of the input filter.

    Perhaps some clarification on the test setup used would be in order.

    When the test were performed all four channels were open circuit, with reference to the schematic screenshot from top left input AC_IN0_P all the way down to AC_IN3_N.

    The reduction in noise were seen when the channel the we had the Oscilloscope connected to Pin 30 U24 (INCM), TP115 were disabled internally on U24 via a SPI software command.

    This led us to believe that the noise were being generated inside the ADC3444.

    This noise reduction only happens when the channel currently being monitored by the oscilloscope were disabled using the software command via SPI interface for that particular channel, this was reproducible on any of the four input channels.

    We did another test this morning were we disabled channels A,B and D and only leaving channel C active and mongering this channel with the oscilloscope the noise seem to remain and only reduces when the channel C is also disabled.  

     

  • 0 in reply to Ben van den Bergh
    Intellectual 435 points

    Hi Cynthia,

    Apologies I had the part number all wrong the device is a ADC3444.

    Could you please fix the heading?

    We made some measurement right on the input of the ADC3444 using the TI EVM and we saw a similar noise pulse but probably at 1/5 of the amplitude than on our design.

    Regards

    Ben

  • 0 in reply to Ben van den Bergh
    TI__Genius 12780 points

    Hi Ben,

    Yes, your correct about the "kickback" noise. Since this ADC has an unbuffered analog input, we see a "glitch" from the sample capacitors that is the same frequency as the sample rate.

    This should not be an issue since the sample "glitch" should have mostly settled through the acquisition phase of the ADC with the help of the passive components on the analog input. Although it looks rather nasty on the scope, it should not effect the performance of the ADC.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Intellectual 435 points

    Hi Dan,

    Thank you for the reply.

    Could you please comment on the following?

    1) Do you have any information regarding exactly where in the 30MHz sample clock period the acquisition is actuality made assuming the rising edge is the start of the period.

    2) Is there anything else we can do to improve the small remaining settling noise, perhaps by lowering the parallel output impedance of the anti aliasing filter?

    Thank you

    Regards

    Ben

  • 0 in reply to Ben van den Bergh
    TI__Genius 12780 points

    Hi Ben,

    1) Do you have any information regarding exactly where in the 30MHz sample clock period the acquisition is actuality made assuming the rising edge is the start of the period.

    The sample begins on the falling edge of the sample clock, and the acquisition time is Fs/2 (16.6 ns with 30 MHz sample clock).

    2) Is there anything else we can do to improve the small remaining settling noise, perhaps by lowering the parallel output impedance of the anti aliasing filter?

    Yes, lowering the impedance should allow for less reflected kickback energy. I would encourage using the TI ADC3444EVM to make filter modifications to see how that impacts, not only the glitch energy at the analog input, but the actual captured ADC data.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Intellectual 435 points

    Hi Dan,

    Thank you very much, your answers were most helpful.

    Regarsd

    Ben