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ADC12DJ3200: damage of JESD204B lane

ttd
Mastermind 8120 points
Part Number: ADC12DJ3200

Dear Technical Support Team,

In the data sheet section 7.4.4., “Powering down the high-speed data outputs for extended times may damage the output serializers…”
There is a description of caution. 

[question 1]
What is the specific time (minutes, days, years?) Of “for extended times”?

[Question 2]
Will damage occur even if there is no input to CLK + / CLK-?

[Question 3]
Is the following setting sufficient as the initial setting sequence to prevent damage for all 16 lanes after the power is turned on?
Are there any other registers that should be set?
(* After setting the following, when operating the ADC again, other JESD parameter settings, SYSREF Calibration, Foreground Calibration
Is expected to be executed. )
(1) SOFT_RESET = 1b @ 000h
(2) JESD_EN = 0b @ 200h
(3) CAL_EN = 0b @ 061h
(4) JEXTRA_A = FFh @ 20Ah, JEXTRA_B = FFh @ 20Bh
(5) CAL_EN = 1b @ 061h
(6) JESD_EN = 1b @ 200h

Best Regards,

ttd

  • 0
    TI__Mastermind 20541 points

    Hi ttd,

    1. Powering down the high speed data output for extended times will result in asymmetric aging which is more of long term effect and can reduce the life time of the device.

    2. No by turning off the clock to the device there will be no damage.

    3. The best option is not applying the clock to ADC to save power and not damage the ADC.

    Regards,

    Neeraj