Part Number: ADC12DJ3200QML-SP
Hi Team, We may need your inputs on this. The datasheet has a note regarding the TSTMP inputs lack of internal biasing...I want to use AC coupling to my system, so how do I need to bias the TSTMP+/- pins.
Hoping for your response.
Thank you.
Regards,
Mark
Hi Mark,
I would recommend to DC couple the TSTMP signal. I would recommend to either use the 1.8V HSTL or SSTL standard IO on the FPGA. Generally the FPGA has internal series 50ohms resistors and the ADC also has 50 Ohms to ground for each leg when TMSTP_LVPECL_EN = 1. So in theory the circuit shown below should work and there shouldn’t be a need to add any component . If the FPGA does not have the Series 50ohms inside the FPGA you can add them on the board on each line.
If you want to AC couple the time stamp signal you bias the common mode voltage on both positive and negative timestamp pins by using the pull up resistor or resistor divider to bring the common mode voltage into the acceptable range of the time stamp pins after the ADC coupling caps on the ADC side.
Regards,
Neeraj
