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AFE5832LP: ISERDESE2 Q1~Q6 are always change when I set dclk delay value from "h00"to "h1F

Neal Zhu
Expert 2470 points
Part Number: AFE5832LP

Hi

FPGA(xilinx,IBUFDS+IDELAYE2+ISERDESE2+vio, according xilinx document "xapp524-serial-lvds-adc-interface.pdf") receive AFE5832LP LVDS data:I change Dclk delay value by VIO of vivado, and get Dclk's ISERDESE2 ouput(Q1~Q6) at the same time.

AFE5832LP configration: ADC_CLK=80MHz,12bit ADC,12bit LVDS,PAT_MODES=Deskew,LVDS 1x,

By set dclk delay value to "h03"(ISERDESE2 Q1~Q6="h00" when set delay"h01"; ISERDESE2 Q1~Q6="h11" when set delay"h05"),I can receive Lvds data corrently"h0555".

but I can't receive lvds data corrently when I download the same bitstream somotimes, "h0555" or other value;      ISERDESE2 Q1~Q6 are always change when I set dclk delay value from "h00"to "h1F", why?

By the way, 

1, Why some Register value are different? such as reg h60/h61/h82/h83...,and they are not descripted in datasheet.

2, can you provide me detailed Register Description or datasheet?

Thanks!

  • 0
    TI__Expert 6040 points

    Hi Neal,

    Thanks for using TI's AFE!

    in your case, 12bit 80MSPS means 960MSPS data rate. it is pretty high for many low cost FPGAs. So the timing margin is a challenging.

    The LVDS timing depends on temperature as well. Thus some time dynamic phase alignment is needed from time to time for archiving the best delay on AFE side or FPGA side. in general, i think FPGA vender has delay cells linked to the DPA procedure.  

    the registers you mentioend are internal debug registers. they are not recommended for use. Thus TI's datasheet doesn't document them.  as i said the delay can to be done in the FPGA side. 

    please also make sure the TX_TRIG signal is given as datasheet 

    9.3.7.2 ADC Synchronization Using TX_TRIG
    The device has multiple PLLs and clock dividers that are used to generate the programmable ADC resolutions
    and LVDS synchronization factors as well as to synchronize LVDS test patterns. The TX_TRIG input is used to
    synchronize clock dividers inside the device. The synchronization achieved using TX_TRIG also enables multiple
    parallel devices to operate synchronously. Additionally, the same ADC alternates between converting two inputs.
    The TX_TRIG signal provides the mechanism to determine the sampling instants of the odd and even input
    signals with respect to the system clock, as shown in Figure 72.

    Thanks!