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ADS54J64: Ramp pattern

Kazuhiko Hirano
Genius 16358 points

Part Number: ADS54J64

Hello,

 

Ramp pattern can be selected by register 91h bit 7-4 = 0100.

But, here, what is the ramp pattern exactly?

The ramp pattern consists of 2’s complement code or offset binary code?

If it is 2’s complement code, the pattern start from 1111,1111,1111,1111b and is incremented by 1b every sample period and eventually reached 0111,1111,1111,1111b, then get back to 1111,1111,1111,1111b next and this cycle repeats?

If it is offset binary code, the pattern start from 0000,0000,0000,0000b and is incremented by 1b every sample period and eventually reached 1111,1111,1111,1111b, then get back to 0000,0000,0000,0000b next and this cycle repeats?

 

Best regards,

 

K.Hirano

  • 0
    TI__Guru* 91947 points

    Hirano,

    I am checking with the design team but after looking at the data sheet, it appears the data can only be offset binary. The pattern would go up to 1111.... then cycle to 0000....

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Genius 16358 points

    Jim,

     

    Thank you for your response.

     

    I received more detailed information from my customer.

    My customer is observing the followings.

    Please confirm if those observations are the expected Ramp pattern behaviors or not.

    They are using Mode 8.

     

    • The Ramp pattern repeats from 0000,0000,0000,0000b to 0000, 0001, 1111, 1111, looks like 9bit length offset binary code.

    • The Ramp pattern is incremented by 2xLSB, like 0, 2, 4, …

    • At Channel A, B, C and D, each phase are different by 2xLSB as follows.

    A: 0, 2, 4, 6, 8, 10, …

    B: 2, 4, 6, 8, 10, 12, …

    C: 4, 6, 8, 10, 12, 14, …

    D: 6, 8, 10, 12, 14, 16, …

     

    Best regards,

     

    K.Hirano

  • 0 in reply to Kazuhiko Hirano
    TI__Guru* 91947 points

    Hirano,

    Design has verified the output data is 2's comp from this device. Depending on what mode the customer is using, the pattern you show is correct for the ramp mode.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Genius 16358 points

    Jim,

     

    Some more confirmations.

     

    Since ADS54J64 is 14bits ADC, the 14bit 2’s complement data is sent from MSB and two zeros are put last two LSBs via JESD as follows, right?

    Bit13, Bit12, Bit11, Bit10, Bit9, Bit8, Bit7, Bit6, Bit5, Bit4, Bit3, Bit2, Bit1, Bit0, Zero, Zero.

     

    But, in case of Ramp pattern, seven zeros are sent first and 9bit ramp data is sent last 9 LSBs?

     

    Best regards,

     

    K.Hirano

  • 0 in reply to Kazuhiko Hirano
    TI__Guru* 91947 points

    Hirano,

    The data order is correct. I am looking into the ramp issue. This is with mode 8 I am assuming.

    Jim

  • 0 in reply to jim s
    TI__Genius 16358 points

    Jeff,

     

    Yes, my customer is using Mode 8.

    Please confirm the correct ramp data format via JESD on Mode 8.

     

    Best regards,

     

    K.Hirano