• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 238 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC122S021: question regarding data read out

Gary Yu
Prodigy 10 points
Part Number: ADC122S021

On the datasheet page 6~ page7, Figure 1 and Figure3, ADD0 will be read at 5th rising edge after /CS low. But the MSB of data seems already shifted out at 5th falling edge after /CS low, ahead of ADD0. Since ADD0 determinate which channel sample date will be send out, the MSB is from which channel? how does the chip know which channel data need to be shifted out?

  • 0
    TI__Mastermind 24940 points

    Hello Gary,

    You are correct, the last bit of the address is clocked in after the the MSB bit is clocked out. But, the three channel address bits determine which input channel will be sampled and converted in the next track/hold cycle, not in the current one.

    For example, in Frame N, channel 1 is selected. But the SDO data in frame N corresponds to the channel selected in Frame N-1, and will not be channel 1 data.

    In the next frame, Frame N+1, the SDO data will correspond to Channel 1.

    Regards

    Cynthia