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DAC34SH84: Xilinx reference design

SM
Expert 1750 points
Part Number: DAC34SH84
Other Parts Discussed in Thread: DAC3484

Hello,

    We are planning to use the DAC34SH84 for a new project. 

I am looking for answers to the following questions and will be grateful for your help:

1) How different is the DAC34SH84 from the DAC3484?

2) The data interface supported is up to 750Mbps, so does it mean that each of the four channels can be fed data at this rate? 

3) Is there a Xilinx reference design provided? Could you please send me a link

4) Iff my FPGA can support a clock of 750MHz then can I generate signal 750MHz with this chip using IQ modulation?

5) An extension of my previous question: So from the chip I can generate two modulated carriers each 750MHz wide. 

6) The data interface is 750Mbps per DAC and since the same 16 bit LVDS interface is fed to two DACs does it mean that the data is 1500Mbps in DDR mode?

7) So I can use a OSERDES from a FPGA to feed data on the 16bit interface

Thanks for your help in understanding the chip,

SM.

  • 0
    TI__Guru* 78174 points

    Hi,

    SM said:
    1) How different is the DAC34SH84 from the DAC3484?

    The DAC34sh84 has 32 LVDS input bus while the DAC3484 only has 16 LVDS input bus. Please see datasheet for detail

    SM said:

    2) The data interface supported is up to 750Mbps, so does it mean that each of the four channels can be fed data at this rate? 

    correct

    SM said:

    3) Is there a Xilinx reference design provided? Could you please send me a link

    see below app note

    SM said:

    4) Iff my FPGA can support a clock of 750MHz then can I generate signal 750MHz with this chip using IQ modulation?

    You FPGA need to support 1.5Gbps of LVDS bus rate. Yes, you can support BW of 750MHz max.

    SM said:

    5) An extension of my previous question: So from the chip I can generate two modulated carriers each 750MHz wide. 

    each channel can support up to 750MHz wide of modulated carrier

    SM said:

    6) The data interface is 750Mbps per DAC and since the same 16 bit LVDS interface is fed to two DACs does it mean that the data is 1500Mbps in DDR mode?

    yes

    SM said:

    7) So I can use a OSERDES from a FPGA to feed data on the 16bit interface

    yes, correct

  • 0 in reply to Kang Hsia
    Expert 1750 points

    Hi Kang,

            Thank you for the quick answers.

    1) Is there a difference in the way the DAC34SH84 and the DAC3484 are to be configured (apart from 16 and 32 bit interfaces)?

    2) Can the complex mixer be used to produce two different outputs on the two DACs or it is to produce I and Q out only?

    3) Can the eval board be used with TSW14J56EVM?

    4) Can complex mixer be used to use produced a modulated carrier at one DAC output only? 

    5) If each of the DAC outputs can operate at 1.5GSps  and used as I,Q sources for an external IQ modulator then can a 1.5GHz BW signal be generated (since I and Q will both have a bw of 750MHz). 

    Thanks again,

  • 0 in reply to SM
    TI__Guru* 78174 points

    Hi,

    1. there are differences. You may refer to the EVM GUI for detail and also the datasheet.

    2. complex mixer is meant to be used with I/Q stream due to the arithmetic.

    3. No, this is not a JESD204 interface. You have to use TSW1400EVM

    5. No, the bandwidth is limited by the first stage FIR. This is then upsampled/filtered to form 1.5GSPS.

    -Kang

  • 0 in reply to Kang Hsia
    Expert 1750 points

    Hi Kang,

         Thank you for the answers.

    You mentioned that each DAC is capable of generating a signal of 750MHz BW.

    Can each of these DAC outputs be frequency translated, for instance can I have one DAC generate a modulated carrier of 10MHz BW centered at 400MHz?

    Regards,

  • 0 in reply to SM
    TI__Guru* 78174 points

    Hi SM,

    sure, that's shouldn't be an issue

    You can do it in two ways:

    1. through the DUC inside your FPGA. If you do so, you will need to make sure the signal BW + carrier location is less than 750MHz to avoid DAC's first stage FIR filter cut-off

    2. use the Complex mixer of the DAC. You will need to send complex signal I/Q for the complex mixer

  • 0 in reply to Kang Hsia
    Expert 1750 points

    Thanks Kang,

    In the first option is the mixing restricted to fs/2?

    The second option produces I x cos(wt) + Q x sin(wt). Wouldn't this produce an image?

  • 0 in reply to SM
    TI__Guru* 78174 points

    Hi SM

    SM said:

    In the first option is the mixing restricted to fs/2?

    Mixing is restricted to Fs/2 only if you are sending real, independent data

    SM said:
    second option produces I x cos(wt) + Q x sin(wt). Wouldn't this produce an image?

    Again, this only applies if you are sending real, independent data.

  • 0 in reply to Kang Hsia
    Expert 1750 points

    Hello Kang,

             Apologies on harping on something that might be very trivial for you.

    1) In the real mixer mode, the up conversion is restricted to fs/2. Am I correct?

    In this mode channel A data (DAC A data) is only used for mixing. 

    2) In complex mixing: one output will be I x cos(wt) + Q x sin(wt) and the other output I x cos(wt) - Q x sin(wt). What is the difference in the outputs in this case when I and Q are centered at 0Hz. 

    Regards,
    SM.

  • 0 in reply to SM
    TI__Guru* 78174 points

    Hi SM

    1. yes, correct. Real, independent data cannot use NCO. If NCO is used, then it need to set to Fs/2

    2. you will see image swap. You have to model it with RF complex mixer in the Matlab to observe this. 

  • 0 in reply to Kang Hsia
    Expert 1750 points

    Hello Kang,

                We have already worked with the DAC3484 and know how to use it (most of it) but now we need to generate wider signal bandwidths and are considering the DAC34SH84. 

    However would it make sense to go for a JESD interface device? Our target frequencies are above the range of the RF sampling DACs so that probably doesn't help us much. 

    The advantages we see with the DAC34SH84 are as follows:

    1) minimal latency (compared to the JESD interface)

    2) probably lower power (16 LVDS pairs running at 750MSps vs two or three JESD lines running at 10Gbps)

    3) Additional cost of the JESD interface (inside the FPGA)

    4) A lower cost FPGA can be used (do not need to have a FPGA that has high speed transceivers)

    Please help us choose the better approach,

    Regards,

    SM

  • 0 in reply to SM
    TI__Guru* 78174 points

    Hi SM,

    Based on my understanding of your end products, I am transferring you to Catalog Converters group within TI as they are better suited on making recommendations for your end products. They will reach out to you to understand your applications better and make appropriate recommendations. 

  • 0 in reply to SM
    TI__Guru* 91947 points

    SM,

    I would determine the cost for each case and make your decision on that as long as both cases meet your requirements. You may need a more expensive board material if using the JESD part based on the serdes rate you select. If you plan on using a Xilinx FPGA, TI is now providing free JESD IP. TI will also have this available for Intel parts in the near future.

    Regards,

    Jim